Extensible Host Controller Interface: Difference between revisions

Revision as of 22:47, 8 February 2021

Revision as of 19:12, 17 March 2021

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=== Power efficiency ===

When USB was originally developed in 1995, it was targeted at desktop platforms to stem the proliferation of connectors that were appearing on PCs, e.g. [[PS/2 connector|PS/2]], [[serial port]], [[parallel port]], Game[[game Portport]], etc., and host power consumption was not an important consideration at the time. Since then, mobile platforms have become the platform of choice, and their batteries have made power consumption a key consideration. The architectures of the legacy USB host controllers (OHCI, UHCI, and EHCI) were very similar in that the "schedule" for the transactions to be performed on the USB were built by software in host memory, and the host controller hardware would continuously read the schedules to determine what transactions needed to be driven on the USB, and when, even if no data was moved. Additionally, in the case of reads from the device, the device was polled each schedule interval, even if there was no data to read.

* The xHCI eliminates host memory based USB transaction schedules, enabling zero host memory activity when there is no USB data movement.

* The xHCI reduces the need for periodic device polling by allowing a USB 3.0 or later device to notify the host controller when it has data available to read, and moves the management of polling USB 2.0 and 1.1 devices that use interrupt transactions from the CPU-driven USB driver to the USB host controller. EHCI, OHCI, and UHCI host controllers would automatically handle polling for the CPU if there are no changes that need to be made and if no device has any interrupts to send but they all rely on the CPU to set the schedule up for the controllers.<ref>{{cite web|url=ftp://ftp.netbsd.org/pub/NetBSD/misc/blymn/uhci11d.pdf |title=UHCI11D.DOC |website=Ftp.netbsd.org |format=PDF |date= |accessdate=2017-01-09}}</ref><ref>{{cite web |url=http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/ehci-specification-for-usb.pdf |title=Archived copy |accessdate=2014-07-02 |url-status=dead |archiveurl=https://web.archive.org/web/20150810175253/http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/ehci-specification-for-usb.pdf |archivedate=2015-08-10 }}</ref><ref>[ftp://ftp.compaq.com/pub/supportinformation/papers/hcir1_0a.pdf] {{dead link|date=January 2017}}</ref> If any USB device using interrupt transactions does have data to send, then an xHCI host controller will send an interrupt to notify the CPU that there is a USB interrupt transaction that needs handling. Since the CPU no longer has to manage the polling of the USB bus, it can spend more time in low power states.