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Undid revision 1020710514 by Locke Cole (talk) consensus format |
Locke Cole (talk | contribs) m nice to see even the seemingly innocent improvements are somehow unworthy of being saved in your crusade to force IEC prefixes on the rest of us... Tag: Reverted |
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** Level 0 (L0) [[Micro-operation|Micro operations]] cache – 6,144 bytes (6 KiB)<ref>{{cite web|url=http://www.anandtech.com/show/6355/intels-haswell-architecture/6 |title=Intel's Haswell Architecture Analyzed: Building a New PC and a New Intel |publisher=AnandTech |access-date=2014-07-31}}</ref> in size
** Level 1 (L1) [[Opcode|Instruction]] cache – 128 KiB in size
** Level 1 (L1) Data cache – 128 KiB in size. Best access speed is around 700 [[GB]]/s<ref name=sisd_qa_f_mem_hsw>{{cite web|url=http://www.sisoftware.co.uk/?d=qa&f=mem_hsw |title=SiSoftware Zone |publisher=Sisoftware.co.uk |access-date=2014-07-31|archive-url=https://web.archive.org/web/20140913231938/http://www.sisoftware.co.uk/?d=qa&f=mem_hsw|archive-date=2014-09-13}}</ref>
** Level 2 (L2) Instruction and data (shared) – 1 [[MiB]] in size. Best access speed is around 200 GB/s<ref name=sisd_qa_f_mem_hsw />
** Level 3 (L3) Shared cache – 6 MiB in size. Best access speed is around 100 GB/s<ref name=sisd_qa_f_mem_hsw />
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