Compressed instruction set: Difference between revisions

Revision as of 11:31, 4 May 2021

Revision as of 14:32, 11 May 2021

Line 1:

A '''compressed instruction set''', or simply '''compressed instructions''', are a variation on a [[microprocessor]]'s [[instruction set architecture]] (ISA) that allows instructions to be represented in a more compact format. In most real-world examples, compressed instructions are 16- bits long in a processor that would otherwise use 32-bit instructions. It is distinct from the concept of [[variable length instructions]], where any instruction can have any length; in a compressed set the instructions are alternatealternative forms for existing 32-bit versions.

The concept was originally introduced in the 1980s by [[Hitachi]] as a way to improve the [[code density]] of their [[SuperH]] [[RISC]] processor design and thereby allow programs to run in smaller amounts of [[main memory]]. Today these smaller instructions are known as SHcompact. As memory of even the smallest systems is now [[order-of-magnitude|orders of magnitude]] larger, this is no longer the main concern; today the advantage is that it reduces the number of accesses to main memory and thereby reduces energy use in [[mobile device]]s. Hitachi's patents were licensed by [[Arm Ltd.]] for their processors, where it was known as "Thumb". Similar systems are found in MIPS16e and Power ISA.