Compressed instruction set: Difference between revisions

Revision as of 14:32, 11 May 2021

Revision as of 15:50, 11 May 2021

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The concept was originally introduced in the 1980s by [[Hitachi]] as a way to improve the [[code density]] of their [[SuperH]] [[RISC]] processor design and thereby allow programs to run in smaller amounts of [[main memory]]. Today these smaller instructions are known as SHcompact. As memory of even the smallest systems is now [[order-of-magnitude|orders of magnitude]] larger, this is no longer the main concern; today the advantage is that it reduces the number of accesses to main memory and thereby reduces energy use in [[mobile device]]s. Hitachi's patents were licensed by [[Arm Ltd.]] for their processors, where it was known as "Thumb". Similar systems are found in MIPS16e and Power ISA.

The introduction of [[64-bit computing]] has led to the term no longer being as widely used; these processors generally use 32-bit instructions and are technically a form of compressed ISA, but as they are mostly modified versions of an older 32-bit ISA from a 32-bit version of the same processor family,; there's is no real compression. The original patents have expired and the concept can be found in a number of modern designs, including the [[RISC-V]], which was designed from the outset to use it.

==Concept==