Compressed instruction set: Difference between revisions

Revision as of 17:54, 11 May 2021

Revision as of 11:05, 12 May 2021

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===Code density===

The downside to the RISC approach is that many instructions simply do not require four bytes. For instance, the [[Logical shift|Logical Shift Left]] instruction shifts the bits in a register to the left, and only requires the instruction opcode and a register number. In the 6502, which has a single arithmetic register A, and thus does not even need a register number, the {{code|ASL}} instruction takes up one byte.{{sfn|Verts|2004}} In theory, MIPS needs only a 6-bit opcode and a 5-bit register number for this same operation, and in theory, could fit the instruction in a 16-bit value. But as is the case for most RISC designs, the instruction still takes up a full 32-bits. As these sorts of instructions are relatively common, RISC programs generally take up more memory than the same program on a variable length processor.{{sfn|Weaver|McKee|2009}}

In the 1980s, when the RISC concept was first emerging, this was a common point of complaint. As the instructions took up more room, the system would have to spend more time reading instructionsinstructiaons from memory. It was suggested these extra accesses might actually slow the program down. Extensive [[benchmarking]] eventually demonstrated RISC was faster in almost all cases, and this argument faded. However, there are cases where memory use remains a concern regardless of performance, and that is in small systems and embedded applications. Even in the early 2000s, the price of [[DRAM]] was enough that cost-sensitive devices had limited memory. It was for this market that [[Hitachi]] developed the [[SuperH]] design.<ref>{{cite web |url=http://resource.renesas.com/lib/eng/e_learnig/sh4/02/index.html |title=Effects of 16-bit instructions |website=Renesas}}</ref>

In the earlier SuperH designs, SH-1 through SH-4, instructions always take up 16-bits. The resulting instruction set has real-world limitations; for instance, it can only perform two-operand math of the form {{code|A {{=}} A + B}}, whereas most processors of the era allowed {{code|A {{=}} B + C}}, the three-operand format. By removing one operand, four bits are removed from the instruction (there are 16 registers, needing 4 bits), although this is at the cost of making math code somewhat more complex to write. For the markets targeted by the SuperH, this was an easy tradeoff to make. A significant advantage of the 16-bit format is that the [[instruction cache]] now holds twice as many instructions for any given amount of [[SRAM]]. This allows the system to perform at higher speeds, although some of that might be mitigated by the use of additional instructions needed to perform operations that a single 3-operand instruction allowed.{{sfn|SuperH|1996}}