Cycles per instruction: Difference between revisions

Revision as of 17:41, 23 May 2021

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# Write-back cycle (WB).

Each stage requires one clock cycle and an instruction passes through the stages sequentially. Without [[Pipelineinstruction (computing)pipelining|pipelining]], in a [[multi-cycle processor]], a new instruction is fetched in stage 1 only after the previous instruction finishes at stage 5, therefore the number of clock cycles it takes to execute an instruction is five (CPI = 5 > 1). In this case, the processor is said to be ''subscalar''. With pipelining, a new instruction is fetched every clock cycle by exploiting [[instruction-level parallelism]], therefore, since one could theoretically have five instructions in the five pipeline stages at once (one instruction per stage), a different instruction would complete stage 5 in every clock cycle and on average the number of clock cycles it takes to execute an instruction is 1 (CPI = 1). In this case, the processor is said to be ''scalar''.

With a single-[[Execution unit|execution-unit]] processor, the best CPI attainable is 1. However, with a multiple-execution-unit processor, one may achieve even better CPI values (CPI < 1). In this case, the processor is said to be ''[[superscalar]]''. To get better CPI values without pipelining, the number of execution units must be greater than the number of stages. For example, with six executions units, six new instructions are fetched in stage 1 only after the six previous instructions finish at stage 5, therefore on average the number of clock cycles it takes to execute an instruction is 5/6 (CPI = 5/6 < 1). To get better CPI values with pipelining, there must be at least two execution units. For example, with two executions units, two new instructions are fetched every clock cycle by exploiting instruction-level parallelism, therefore two different instructions would complete stage 5 in every clock cycle and on average the number of clock cycles it takes to execute an instruction is 1/2 (CPI = 1/2 < 1).