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#REDIRECT [[Ivy Bridge (microarchitecture)#IVY-BRIDGE-E]] {{R to section}}
{{Infobox CPU
| name = Ivy Bridge-E
| created = September 10, 2013
| cores = up to 15 (physical)<br> up to 30 (logical)
| transistors = up to 4.3B [[22 nanometer|22 nm]] (S1)
| l1cache = 32 KB per core
| l2cache = 256 KB per core
| l3cache = up to 37.5 MB shared
| cpuid = 0306Exh
| code = 80633, 80636, 80634, 80635
| dmi = 5.00 GT/s
| arch1 = [[Ivy_Bridge_(microarchitecture)|Ivy Bridge]]
| sock1 = [[LGA 2011]], [[LGA 1356]], [[LGA 2011-1]]
| predecessor = [[Sandy Bridge-E]]
| successor = [[Haswell-E]]
|size-from=[[22 nm]]|application=servers, workstations, high-end desktops|fastest=3.7|designfirm=[[Intel Corporation]]}}'''Intel Ivy Bridge-based Xeon microprocessors''' (also known as '''Ivy Bridge-E''') is the follow-up to [[Sandy Bridge-E]], using the same CPU core as the [[Ivy Bridge (microarchitecture)|Ivy Bridge]] processor, but in [[LGA 2011]], [[LGA 1356]] and [[LGA 2011-1]]<ref name="intel-xeon-e7-v2" /> packages for workstations and servers.
There are five different families of Xeon processors that were based on Sandy Bridge architecture:
* '''Ivy Bridge-E''' uses [[LGA 2011]] socket and was branded as '''Core i7 Extreme Edition''' and '''Core i7''' high-end desktop (HEDT) processors, despite sharing many similarities with Xeon E5 models.
* '''Ivy Bridge-EP''' which also uses [[LGA 2011]] socket for the Xeon E5 models aimed at high-end servers and workstations. It supports motherboards equipped with up to 4 sockets.
* '''Ivy Bridge-EX''' introduces new [[LGA 2011|LGA 2011-1]] socket and features up to 15 cores. It supports motherboards equipped with up to 8 sockets.
* '''Ivy Bridge-EN''' uses a smaller [[LGA 1356]] socket for low-end and dual-processor servers on certain Xeon E5 and Pentium branded models.
* '''Ivy Bridge''' '''Xeon''' with [[LGA 1155]] socket were mostly identical to its desktop counterparts apart from the missing [[IGPU]] despite branded as Xeon processors.
* '''Gladden''' with BGA 1284 package and was intended for embedded applications.
== Features ==
*Dual memory controllers for Ivy Bridge-EP and Ivy Bridge-EX<ref name="anandtech-xeon-e5-2600-v2">{{cite web|date=September 17, 2013|title=Intel's Xeon E5-2600 V2: 12-core Ivy Bridge EP for Servers|url=http://www.anandtech.com/show/7285/intel-xeon-e5-2600-v2-12-core-ivy-bridge-ep|access-date=January 21, 2014|publisher=AnandTech}}</ref>
* Up to 12 CPU cores and 30 MB of L3 cache for Ivy Bridge-EP<ref name="anandtech-xeon-e5-2600-v2" />
* Up to 15 CPU cores and 37.5 MB L3 cache for Ivy Bridge-EX<ref>{{cite web|title=Some details of Ivy Bridge-EX processors|url=http://www.cpu-world.com/news_2013/2013100101_Some_details_of_Ivy_Bridge-EX_processors.html|access-date=October 12, 2013|publisher=Cpu-world.com}}</ref> (released on February 18, 2014 as Xeon E7 v2<ref>{{cite web|author=Charlie Demerjian|title=Intel releases Ivy Bridge-EX now known as Xeon E7 v2|url=http://semiaccurate.com/2014/02/18/intel-releases-ivy-bridge-ex-now-known-xeon-e7-v2/|access-date=February 19, 2014|publisher=SemiAccurate}}</ref>)
* Thermal design power between 50 W and 155 W<ref>{{cite web|date=February 2, 2014|title=Intel Xeon E7 'Ivy Bridge-EX' Lineup Detailed – Xeon E7-8890 V2 'Ivy Town' Chip With 15 Cores and 37.5 MB LLC|url=http://wccftech.com/intel-xeon-e7-ivy-bridgeex-lineup-detailed-xeon-e78890-v2-ivy-town-chip-15-cores-375-mb-llc/|access-date=February 16, 2014|publisher=Wccftech.com}}</ref>
* Support for up to eight [[DIMM]]s of DDR3-1866 memory per socket, with reductions in memory speed depending on the number of DIMMs per [[Multi-channel memory architecture|channel]]<ref>{{cite web|author=Johan De Gelas|date=December 19, 2013|title=Server Buying Decisions: Memory|url=http://www.anandtech.com/show/7479/server-buying-decisions-memory/2|access-date=September 9, 2014|publisher=[[AnandTech]]}}</ref><ref>{{cite web|date=November 14, 2013|title=Fujitsu PRIMERGY Servers Memory Performance of Xeon E5-2600 v2 (Ivy Bridge-EP) based Systems|url=http://globalsp.ts.fujitsu.com/dmsp/Publications/public/wp-ivy-bridge-ep-memory-performance-ww-en.pdf|access-date=September 9, 2014|website=fujitsu.com|pages=4–5}}</ref><ref>{{cite web|author=Jason Fan|year=2013|title=The importance of proper memory configuration for optimal performance (Intel Reference – E5-2600 v2 DDR3 RDIMM Memory Speeds; Intel Reference – E5-2600 v2 DDR3 LRDIMM & ECC UDIMM Memory Speeds)|url=http://www.worldhostingdays.com/downloads/2013-china/mF1a.pdf|url-status=dead|archive-url=https://web.archive.org/web/20140910200016/http://www.worldhostingdays.com/downloads/2013-china/mF1a.pdf|archive-date=September 10, 2014|access-date=September 9, 2014|website=worldhostingdays.com|publisher=[[Kingston Technology]]|pages=7–8|df=dmy-all}}</ref>
* No integrated GPU
* Ivy Bridge-EP introduced new hardware support for interrupt virtualization, branded as [[APICv]].<ref>{{cite web|author=Khang Nguyen|date=December 17, 2013|title=APIC Virtualization Performance Testing and Iozone|url=https://software.intel.com/en-us/blogs/2013/12/17/apic-virtualization-performance-testing-and-iozone|access-date=July 12, 2014|website=software.intel.com}}</ref><ref>{{cite web|date=March 14, 2014|title=Product Brief Intel Xeon Processor E5-4600 v2 Product Family|url=http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/xeon-e5-4600-v2-brief.pdf|access-date=July 12, 2014|publisher=Intel}}</ref>
== Models and steppings ==
The basic Ivy Bridge-E is a single-socket processor sold as Core i7-49xx and is only available in the six-core S1 [[Stepping level|stepping]], with some versions limited to four active cores.
There are in fact three die "flavors" for the Ivy Bridge-EP, meaning that they are manufactured and organized differently, according to the number of cores an Ivy Bridge-EP CPU includes:<ref>{{cite web|last=Novakovic |first=Nebojsa |url=http://vr-zone.com/articles/ivy-bridge-ep-xeon-e5-gets-2013-refresh/56672.html |title=Ivy Bridge-EP: Xeon E5 gets its 2013 refresh |website=VR-Zone.com |date=February 12, 2014 |access-date=February 16, 2014}}</ref>
* The largest is an up-to-12-core die organized as three four-core columns with up to 30 MB L3 cache in two banks between the cores; these cores are linked by three rings of interconnects.
* The intermediate is an up-to-10-core die organized as two five-core columns with up to 25 MB L3 cache in a single bank between the cores; the cores are linked by two rings of interconnects.
* The smallest is an up-to-six-core die organized as two three-core columns with up to 15 MB L3 cache in a single bank between the cores; the cores are linked by two rings of interconnects.
Ivy Bridge-EX has up to 15 cores and scales to 8 sockets. The 15-core die is organized into three columns of five cores, with three interconnect rings connecting two columns per ring; each five-core column has a separate L3 cache.<ref name="theregister-15-core-xeon">{{cite web |url=https://www.theregister.co.uk/2014/02/18/intel_releases_mission_critical_two_four_and_eight_socket_xeon_e7_v2_line/ |title=Better Late than Never: Monster 15-Core Xeon Chips Let Loose by Intel |website=The Register |date=February 18, 2014 |access-date=February 20, 2014}}</ref>
{| class="wikitable sortable"
|-
! Die code name
! CPUID
! Stepping
! Die size
! Transistors
! Cores
! L3 cache
! Socket
|-
| Ivy Bridge-E-6
| rowspan=9| <tt>0x0306Ex</tt>
| rowspan=3| S1
| rowspan=4| 256.5 mm²
| rowspan=4| 1.86 billion
| rowspan=4| {{0}}6
| rowspan=4| 15 MB
| LGA 2011
|-
| Ivy Bridge-EN-6
| LGA 1356
|-
| Ivy Bridge-EP-6
| LGA 2011
|-
| Ivy Bridge-EX-6
| D1
| LGA 2011-1
|-
| Ivy Bridge-EN-10
| rowspan=2| M1
| rowspan=3| 341 mm²
| rowspan=3| 2.89 billion
| rowspan=3| 10
| rowspan=3| 25 MB
| LGA 1356
|-
| Ivy Bridge-EP-10
| LGA 2011
|-
| Ivy Bridge-EX-10
| D1
| LGA 2011-1
|-
| Ivy Bridge-EP-12
| C1
| rowspan=2| 541 mm²
| rowspan=2| 4.31 billion
| 12
| 30 MB
| LGA 2011
|-
| Ivy Bridge-EX-15
| D1
| 15
| 37.5 MB
| LGA 2011-1
|}
{| class="wikitable sortable"
|-
! Code name || Brand name (list) !! Cores !! L3 cache !! Socket || TDP || I/O Bus
|-
| rowspan=2 | Ivy Bridge-E
| [[List of Intel Core i7 microprocessors#"Ivy Bridge-E" (22 nm)|Core i7-48xx]]
| 4 || 10 MB || 1×LGA 2011 || 130 W || DMI
|-
| [[List of Intel Core i7 microprocessors#"Ivy Bridge-E" (22 nm)|Core i7-49xx]]
| 6 || 12–15 MB || 1×LGA 2011 || 130 W || DMI
|-
| rowspan=3 | Ivy Bridge-EN
| [[List of Intel Xeon microprocessors#"Ivy Bridge-EN" (22 nm) Entry|Xeon E5-14xx v2]] || 4–6 || 10–15 MB || 1×LGA 1356 || 60–80 W || DMI
|-
| [[List of Intel Xeon microprocessors#"Ivy Bridge-EN" (22 nm) Entry 2|Xeon E5-24xx v2]]
| 4–10 || 10–25 MB || 2×LGA 1356 || 50–95 W || DMI+QPI
|-
| [[List of Intel Pentium microprocessors#"Ivy Bridge-EN" (22 nm)|Pentium 14xx v2]] || 2 || 6 MB || 1×LGA 1356 || 40–80 W || DMI
|-
| rowspan=4 | Ivy Bridge-EP
| [[List of Intel Xeon microprocessors#"Ivy Bridge-EP" (22 nm) Efficient Performance|Xeon E5-16xx v2]]
| 4–8 || 10–15 MB || 1×LGA 2011 || 130 W || DMI
|-
| [[List of Intel Xeon microprocessors#"Ivy Bridge-EP" (22 nm) Efficient Performance 2|Xeon E5-26xx v2]]
| 4–12 || 10–30 MB || 2×LGA 2011 || 80–150 W || DMI+2×QPI
|-
| [[List of Intel Xeon microprocessors#"Ivy Bridge-EP" (22 nm) Efficient Performance 2|Xeon E5-26xxL v2]]
| 6–10 || 15–25 MB || 2×LGA 2011 || 50–70 W || DMI+2×QPI
|-
| [[List of Intel Xeon microprocessors#"Ivy Bridge-EP" (22 nm) Efficient Performance 3|Xeon E5-46xx v2]]
| 4–12 || 10–30 MB || 4×LGA 2011 || 70–130 W || DMI+2×QPI
|-
| rowspan=3 | Ivy Bridge-EX
| [[List of Intel Xeon microprocessors#Xeon E7-28xx v2 (dual-processor)|Xeon E7-28xx v2]]
| 12-15 || 24–37.5 MB || 2×LGA 2011-1 || 105–155 W || DMI+3×QPI
|-
| [[List of Intel Xeon microprocessors#Xeon E7-48xx v2 (quad-processor)|Xeon E7-48xx v2]]
| 6-15 || 12–37.5 MB || 4×LGA 2011-1 || 105–155 W || DMI+3×QPI
|-
| [[List of Intel Xeon microprocessors#Xeon E7-88xx v2 (octa-processor)|Xeon E7-88xx v2]]
| 6-15 || 24–37.5 MB || 8×LGA 2011-1 || 105–155 W || DMI+3×QPI
|}
== Ivy Bridge-E and Ivy Bridge-EP ==
== Ivy Bridge EX ==
== Ivy Bridge EN ==
| 