Computer security compromised by hardware failure: Difference between revisions

Revision as of 05:01, 21 August 2021

Revision as of 05:03, 21 August 2021

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=== Cache attack ===

* {{cite book| last1 = Osvik | first1 = Dag Arne | title = Topics in Cryptology – CT-RSA 2006 | last2 = Shamir | first2 = Adi | last3 = Tromer | first3 = Eran | book-title = Lecture Notes in Computer Science | volume = 3860 | pages = 1–20 | periodical = Topics in Cryptology CT-RSA | publisher = Springer-Verlag Berlin, Heidelberg | place = San Jose, California, USA | citeseerx = 10.1.1.60.1857 | year = 2006 | issn = 0302-9743 | doi = 10.1007/11605805_1 | isbn = 978-3-540-31033-4 | ref = Sha1| chapter = Cache Attacks and Countermeasures: The Case of AES | series = Lecture Notes in Computer Science }}

* {{Citation| last1 = Page | first1 = Daniel | title = Partitioned cache architecture as a side-channel defence mechanism | periodical = Cryptology ePrint Archive | url = http://eprint.iacr.org/2005/280.pdf | year = 2005 | ref = Pag1 }}

* {{cite book| last1 = Bertoni | first1 = Guido | title = International Conference on Information Technology: Coding and Computing (ITCC'05) – Volume II | last2 = Zaccaria | first2 = Vittorio | last3 = Breveglieri | first3 = Luca | last4 = Monchiero | first4 = Matteo | last5 = Palermo | first5 = Gianluca | place = Washington, DC, USA | volume = 1 | pages = 586–591 | periodical = International Conference on Information Technology: Coding and Computing (ITCC'05) | publisher = IEEE Computer Society, Los Alamitos, California, USA | chapter-url = http://home.dei.polimi.it/gpalermo/papers/ITCC05.pdf | year = 2005 | doi = 10.1109/ITCC.2005.62 | isbn = 978-0-7695-2315-6 | ref = Bert1 | chapter = AES power attack based on induced cache miss and countermeasure | citeseerx = 10.1.1.452.3319 | s2cid = 9364961 }}