Revision as of 09:15, 17 October 2021 edit HMSLavender (talk \| contribs) Extended confirmed users, Pending changes reviewers, Rollbackers 66,407 edits Restoring revision 1045180888 by I dream of horses: rv further (RW 16.1) Tags: RW Undo ← Previous edit		Revision as of 09:13, 30 August 2022 edit undo Frap (talk \| contribs) Extended confirmed users, File movers, Pending changes reviewers, Rollbackers 35,588 edits m →Recent implementation models Next edit →
Line 99: === AMD Zen microarchitecture (2017) === * L1 cache – 32 kB data & 64 kB instruction per core, 4-way * L2 cache – 512 kB per core, 4-way inclusive Line 105 ⟶ 104: === AMD Zen 2 microarchitecture (2019) === * L1 cache – 32 kB data & 32 kB instruction per core, 8-way * L2 cache – 512 kB per core, 8-way inclusive * L3 cache – 16 MB local per 4-core CCX, 2 CCXs per chiplet, 16-way non-inclusive. Up to 64 MB on desktop CPUs and 256 MB on server CPUs === IBM ~~Power~~POWER7 7(2010) === * L1 cache (instruction and data) – each 64-banked, each bank has 2rd+1wr ports 32 kB, 8-way associative, 128B block, write through * L2 cache – 256 kB, 8-way, 128B block, write back, inclusive of L1, 2 ns access latency

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