Memory segmentation: Difference between revisions

Revision as of 19:45, 31 December 2021

Revision as of 01:23, 2 January 2022

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==Examples==

===S/370 architecture===

In the [[IBM System/370]] models{{efn|Models 115, 125, 135, 138, 145, 148, 155 II, 158, 165 II and 168}} with virtual storage<ref name=S370>{{cite manual

| title = IBM System/370 Principles of Operation

| id = GA22-7000-4

| edition = Fourth

| date = September 1974

| section = Dynamic Address Translation

| url = http://www.bitsavers.org/pdf/ibm/370/princOps/GA22-7000-4_370_Principles_Of_Operation_Sep75.pdf

| section-url = http://www.bitsavers.org/pdf/ibm/370/princOps/GA22-7000-4_370_Principles_Of_Operation_Sep75.pdf#page=57

| format = PDF

| workpages = Systems57-68

| url = http://www.bitsavers.org/pdf/ibm/370/princOps/GA22-7000-4_370_Principles_Of_Operation_Sep75.pdf

| publisher = IBM

| idwork = SA22-7085-1Systems

| publisher = IBM

}}

<!-- This is the most recent version that I could find in bitsavers -->

</ref> models{{efn|Models 115, 125, 135, 138, 145, 148, 155 II, 158, 165 II and 168}} with virtual storage and 24-bit addresses, [[control register]] 0 specifies a segment size of either 64 KiB or 1 MiB and a page size of either 2 KiB or 4 KiB; control register 1 specifies the length and real address of the segment table.

</ref><ref name=S370-10>{{cite manual

| title = IBM System/370 Extended Architecture Principles of Operation

| id = GA22-7000-10

| edition = SecondEleventh

| date = JanuarySeptember 1987

| section = Dynamic Address Translation

| pages = 3-20-3-38

| publisher = IBM

}}

</ref> (DAT) and 24-bit addresses, [[control register]] 0 specifies a segment size of either 64 KiB or 1 MiB and a page size of either 2 KiB or 4 KiB; control register 1 contains a Segment Table Designator (STD), which specifies the length and real address of the segment table. Each segment table entry contains a page table ___location, a page table length and an invalid bit. IBM later expanded the address size to 31 bits and added two bits to the segment table entries:

;Segment-Protection Bit

:Segment is read-only

;Common-Segment Bit

:The segment is shared between address spaces; this bit is set to optimize TLB use

Each of IBM's DAT implementations includes a translation cache, which IBM called a Translation Lookaside Buffer (TLB). While Principles of Operation discusses the TLB in general terms, the details are not part of the architecture and vary from model to model.

Starting with the [[IBM 303X|3031, 3032 and 3033]] processor complexes, IBM offered a feature called ''Dual-address Space'' (DAS)<ref name=S370-XA>{{cite manual

| title = IBM System/370 Extended Architecture Principles of Operation

| id = SA22-7085-1

| edition = Second

| date = January 1987

| url = http://bitsavers.org/pdf/ibm/370/princOps/SA22-7085-1_370-XA_Principles_of_Operation_Jan87.pdf

| publisher = IBM

Starting with the [[IBM 303X|3031, 3032 and 3033]] processor complexes, IBM offered a feature called ''Dual-address Space''<ref (name=S370-10/>{{rp|at=Dual-Address-Space Control|pp=5-13-5-17}}{{rp|at=DAS) Authorization Mechanisms|pp=5-17-5-20}}{{rp|at=PC-Number Translation|pp=5-21-5-24}}<ref name=S370-XA>{{cite manual

| title = IBM System/370 Extended Architecture Principles of Operation

| id = SA22-7085-1

| formatedition = PDFSecond

| date = January 1987

| section = Address spaces

| section-url = http://bitsavers.org/pdf/ibm/370/princOps/SA22-7085-1_370-XA_Principles_of_Operation_Jan87.pdf#page=40

| pages = 3-13-3-14

| url = http://bitsavers.org/pdf/ibm/370/princOps/SA22-7085-1_370-XA_Principles_of_Operation_Jan87.pdf

| publisher = IBM

}}

</ref> that(DAS), which allowedallows a program to switch between the translation tables for two different address spaces, referedreferred to as ''primary address space'' (CR1) and ''secondary address space'' (CR7), and to move data between the address spaces subject to protection key. DAS supportedsupports a translation tablestable to convert a 16-bit address space number (ASN) to a segment table andan lengthSTD, with privileged instructions to load the segment table informationSTD into CR1 (primary) or CR7 (secondary).

===x86 architecture===