Depletion-load NMOS logic: Difference between revisions

Revision as of 02:01, 15 March 2022

Revision as of 02:01, 15 March 2022

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Early work on nMOS [[integrated circuit]] (IC) technology was presented in a brief [[IBM]] paper at [[ISSCC]] in 1969. [[Hewlett-Packard]] then started to develop nMOS IC technology to get the promising speed and easy interfacing for its [[calculator]] business.<ref>These [[calculator]]s (like the [[Datapoint 2200]] and others) were in many ways small [[desktop computer]]s, but preceded the [[Apple II]] and the [[IBM PC]] by many years.</ref> Tom Haswell at HP eventually solved many problems by using purer [[raw material]]s (especially aluminum for interconnects) and by adding a bias voltage to make the [[threshold voltage|gate threshold]] large enough; this ''back-gate bias'' remained a ''de facto'' standard solution to (mainly) [[sodium]] contaminants in the gates until the development of [[ion implantation]] (see below). Already by 1970, HP was making good enough nMOS ICs and had characterized it enough so that Dave Maitland was able to write an article about nMOS in the December, 1970 issue of Electronics magazine. However, nMOS remained uncommon in the rest of the semiconductor industry until 1973.<ref>''Shown by its mere mention in a large roundup article written by GE engineer Herman Schmid that appeared in the December, 1972 issue of IEEE Transactions on Manufacturing Technology. Although it cites Maitland’s 1970 article in Electronics, Schmid’s article does not discuss nMOS fabrication in detail but it does cover pMOS and even CMOS fabrication extensively.''</ref>

The production-ready nMOS process enabled HP to develop the industry’s first 4-kbit IC [[Read-only memory|ROM]]. [[Motorola]] eventually served as a second source for these products and so became one of the first commercial semiconductor vendors to master the nMOS process, thanks to Hewlett-Packard. A while later, the [[startup company]] [[Intel]] announced a 1-kbit pMOS DRAM, called ''1102'', developed as a custom product for [[Honeywell]] (an attempt to replace magnetic [[core memory]] in their [[mainframe computer]]s). HP’s calculator engineers, who wanted a similar but more robust product for the [[HP 9800 series|9800 series]] calculators, contributed IC fabrication experience from their 4-kbit ROM project to help improve Intel DRAM’s reliability, operating-voltage, and temperature range. These efforts contributed to the heavily enhanced ''Intel 1103'' 1-kbit pMOS DRAM, which was the world’s first commercially available [[DRAM]] IC. It was formally introduced in October 1970, and became Intel’s first really successful product.<ref>{{cite web|url=http://www.hp9825.com/html/prologues.html |title=Prologues |publisher=Hp9825.com |date= |accessdate=2022-03-15}}</ref>

===Depletion-mode transistors===

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The first depletion-load nMOS circuits were pioneered and made by the [[DRAM]] manufacturer [[Mostek]], which made depletion-mode transistors available for the design of the original [[Zilog Z80]] in 1975–76.<ref>''Zilog relied on [[Mostek]] and [[Synertek]] to produce the Z80 and other chips before their own production facilities were ready.''</ref> Mostek had the [[ion implantation]] equipment needed to create a [[doping (semiconductor)|doping profile]] more precise than possible with [[diffusion]] methods, so that the [[threshold voltage]] of the load transistors could be adjusted reliably. At Intel, depletion load was introduced in 1974 by Federico Faggin, an ex-Fairchild engineer and later the founder of [[Zilog]]. Depletion-load was first employed for a redesign of one of Intel's most important products at the time, a +5V-only 1Kbit nMOS [[Static random-access memory|SRAM]] called the ''2102'' (using more than 6000 transistors<ref>''Each bit demands six transistors in a typical [[static RAM]].''</ref>). The result of this redesign was the significantly faster ''2102A'', where the highest performing versions of the chip had access times of less than 100ns, taking MOS memories close to the speed of bipolar RAMs for the first time.<ref>''See for instance: http://www.intel4004.com/sgate.htm or http://archive.computerhistory.org/resources/text/Oral_History/Faggin_Federico/Faggin_Federico_1_2_3.oral_history.2004.102658025.pdf'' {{Webarchive|url=https://web.archive.org/web/20170110232713/http://archive.computerhistory.org/resources/text/Oral_History/Faggin_Federico/Faggin_Federico_1_2_3.oral_history.2004.102658025.pdf |date=2017-01-10 }}</ref>

Depletion-load nMOS processes were also used by several other manufacturers to produce many incarnations of popular 8-bit, 16-bit, and 32-bit CPUs. Similarly to early pMOS and nMOS CPU designs using [[Field-effectChannel (transistor#FET operation)|enhancement mode]] MOSFETs as loads, depletion-load nMOS designs typically employed various types of [[dynamic logic (digital logic)|dynamic logic]] (rather than just static gates) or [[Pass transistor logic|pass transistor]]s used as dynamic [[latch (electronics)|clocked latch]]es. These techniques can enhance the area-economy considerably although the effect on the speed is complex. Processors built with depletion-load nMOS circuitry include the [[Motorola 6800|6800]] (in later versions<ref name = "M6800 redesign">{{Cite journal| title = Motorola Redesigns 6800 | journal = Microcomputer Digest | volume = 3 | issue = 2 | page =4 | publisher = Microcomputer Associates | ___location = Santa Clara, CA | date = August 1976 | url = http://www.bitsavers.org/pdf/microcomputerAssociates/Microcomputer_Digest_v03n02_Aug76.pdf}} "Motorola is redesigning the M6800 microprocessor family by adding depletion loads to increase speed and reduce the 6800 CPU size to 160 mils."</ref>), the [[6502]], [[Signetics 2650]], [[8085]], [[6809]], [[8086]], [[Z8000]], [[NS32016]], and many others (whether or not the HMOS processors below are included, as special cases).

A large number of support and peripheral ICs were also implemented using (often static) depletion-load based circuitry. However,