Atmel AVR instruction set: Difference between revisions

Revision as of 20:38, 8 June 2022

Revision as of 20:48, 8 June 2022

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| (Identical to minimal core, except for reduced CPU register set{{note label|reduced|a|a}})

| (Identical to classic core with up to 8K, except for reduced CPU register set{{note label|reduced|a|a}})

| Identical to classic core with up to 8K, with the following exceptions:{{aligned table|cols=2|col1style=font-family:monospace;|LPM|(removed)|LDD|(removed)|STD|(removed)|LD|(also accesses program memory)|LDS
STS|(differentaccess bitis pattern)|STS|(differentlimited to the first 128 bytes bitof patternSRAM)||Reduced CPU register set{{note label|reduced|a|a}}}}

| (Identical to enhanced core with up to 128K, except for reduced CPU register set{{note label|reduced|a|a}})

|}