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[[File:ZX81 ULA.jpg|thumb|Sinclair ZX81 ULA]]
A '''gate array''' is an approach to the design and manufacture of [[application-specific integrated
Similar technologies have also been employed to design and manufacture analog, analog-digital, and structured arrays, but, in general, these are not called gate arrays.
Gate arrays have also been known as
==
A gate array is a prefabricated silicon chip with most [[transistor]]s having no predetermined function. These transistors can be connected by metal layers to form standard [[Negated AND gate|NAND]] or [[NOR gate|NOR]] [[logic gate]]s. These logic gates can then be further interconnected into a complete circuit on the same or later metal layers. Creation of a circuit with a specified function is accomplished by adding this final layer or layers of metal interconnects to the chip late in the manufacturing process, allowing the function of the chip to be customized as desired. These layers are analogous to the copper layers of a [[printed circuit board]].▼
=== Development ===▼
The earliest gate arrays comprised [[bipolar transistors]], usually configured as high performance [[transistor–transistor logic]], [[emitter-coupled logic]] or [[current-mode logic]] logic configurations. [[CMOS]] (complementary [[metal-oxide-semiconductor]]) gate arrays were later developed and came to dominate the industry.▼
Gate array master slices with unfinished chips arrayed across a [[wafer (electronics)|wafer]] are usually prefabricated and stockpiled in large quantities regardless of customer orders. The design and fabrication according to the individual customer specifications can be finished in a shorter time than [[standard cell]] or [[full custom]] design. The gate array approach reduces the non recurring engineering [[Photomask|mask]] costs as fewer custom masks need to be produced. In addition, manufacturing test tooling lead time and costs are reduced - the same test fixtures can be used for all gate array products manufactured on the same [[Die (integrated circuit)|die]] size. Gate arrays were the predecessor of the more complex [[Structured ASIC platform|structured ASIC]]; unlike gate arrays, structured ASICs tend to include predefined or configurable memories and/or analog blocks.▼
An application circuit must be built on a gate array that has enough gates, wiring and I/O pins. Since requirements vary, gate arrays usually come in families, with larger members having more of all resources, but correspondingly more expensive. While the designer can fairly easily count how many gates and I/Os pins are needed, the number of routing tracks needed may vary considerably even among designs with the same amount of logic. (For example, a [[crossbar switch]] requires much more routing than a [[systolic array]] with the same gate count.) Since unused routing tracks increase the cost (and decrease the performance) of the part without providing any benefit, gate array manufacturers try to provide just enough tracks so that most designs that will fit in terms of gates and I/O pins can be routed. This is determined by estimates such as those derived from [[Rent's rule]] or by experiments with existing designs.▼
The main drawbacks of gate arrays are their somewhat lower density and performance compared with other approaches to ASIC design. However this style is often a viable approach for low production volumes.▼
▲===Development===
Gate arrays had several concurrent development paths. [[Ferranti]] in the UK pioneered commercializing [[bipolar transistor|bipolar]] ULA technology,<ref name="bteng198307">{{ cite journal | url=https://archive.org/details/bte-198307/page/n19/mode/2up | title=The Use of Gate Arrays in Telecommunications | journal=British Telecommunications Engineering | last1=Grierson | first1=J. R. | date=July 1983 | access-date=26 February 2021 | volume=2 | issue=2 | pages=78-80 | issn=0262-401X | quote=In the UK, Ferranti, with their bipolar collector diffused isolation (CDI) arrays, pioneered the commercial use of gate arrays and for many years this was by far the most widely used technology. }}</ref> offering circuits of "100 to 10,000 gates and above" by 1983.<ref name="btj198301">{{ cite news | url=https://archive.org/details/btj-198301/page/n71/mode/1up | title=Everybody's talking about Ferranti ICs. | work=British Telecom Journal | volume=3 | issue=4 | date=January 1983 | access-date=23 January 2021 }}</ref><ref name="ferranti_quickref">{{ cite book | url=https://archive.org/details/FerrantiQ.RefULA1984/page/n1/mode/1up | title=Ferranti Discrete and Integrated Circuits Quick Reference Guide | publisher=Ferranti plc. | date=1982 | access-date=23 February 2021 | pages=IC4 }}</ref> The company's early lead in semi-custom chips, with the initial application of a ULA integrated circuit involving a camera from [[Rollei]] in 1972, expanding to "practically all European camera manufacturers" as users of the technology, led to the company's dominance in this particular market throughout the 1970s. However, by 1982, as many as 30 companies had started to compete with Ferranti, reducing the company's market share to around 30 percent. Ferranti's "major competitors" were other British companies such as Marconi and Plessey, both of which had licensed technology from another British company, Micro Circuit Engineering.<ref name="heidelberg19821006_ics">{{ cite magazine | url=https://archive.org/details/jprs-report_jprs-82727/page/10/mode/2up | title=Great Britain Develops Semicustom and Custom ICs | magazine=Heidelberg Elektronik Industrie | date=6 October 1982 | access-date=4 March 2022 | last1=Turmaine | first1=Bradley | pages=43-46 }}</ref> A contemporary initiative, UK5000, also sought to produce a CMOS gate array with "5,000 usable gates", with involvement from [[British Telecom]] and a number of other major British technology companies.<ref name="bteng198610_silicon">{{ cite journal | url=https://archive.org/details/bte-198610/page/n41/mode/2up | title=Silicon Micro-Electronics at British Telecom Research Laboratories | journal=British Telecommunications Engineering | date=October 1986 | access-date=4 March 2022 | pages=230-236 }}</ref>
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After a falling out with IMI, Robert Lipp went on to start California Devices, Inc. (CDI) in 1978 with two silent partners, Bernie Aronson and Brian Tighe. CDI quickly developed a product line competitive to IMI and shortly thereafter a 5 micron silicon gate single layer product line with densities up to 1,200 gates. A couple of years later CDI followed up with "channel-less" gate arrays that reduced the row blockages caused by a more complex silicon underlayer that pre-wired the individual transistor connections to locations needed for common logic functions, simplifying the first level metal interconnect. This increased chip densities 40%, significantly reducing manufacturing costs.<ref name=":1" />
=== Innovation ===
[[File:Timex Sinclair 1000 Motherboard BL (cropped Ferranti ULA).jpg|thumb|Ferranti {{abbr|ULA|Uncommitted Logic Array}} 2C210E on a [[Timex Sinclair 1000]] motherboard]]▼
Early gate arrays were low performance and relatively large and expensive compared to state-of-the-art n-MOS technology then being used for custom chips. CMOS technology was being driven by very low power applications such as watch chips and battery operated portable instrumentation, not performance. They were also well under the performance of the existing dominant logic technology, transistor–transistor logic families. However, there were many niche applications where they were invaluable, particularly in low power, size reduction, portable and aerospace applications as well as time-to-market sensitive products. Even these small arrays could replace a board full of transistor–transistor logic gates if performance were not an issue. A common application was combining a number of smaller circuits that were supporting a larger LSI circuit on a board was affectionately known as "garbage collection". And the low cost of development and custom tooling made the technology available to the most modest budgets. Early gate arrays played a large part in the [[Citizens band radio#1970s popularity|CB craze in the 1970s]] as well as a vehicle for the introduction of other later mass-produced products such as modems and cell phones.
▲[[File:Timex Sinclair 1000 Motherboard BL (cropped Ferranti ULA).jpg|thumb|Ferranti {{abbr|ULA|Uncommitted Logic Array}} 2C210E on a [[Timex Sinclair 1000]] motherboard]]
By the early 1980s gate arrays were starting to move out of their niche applications to the general market. Several factors in technology and markets were converging. Size and performance were increasing; automation was maturing; technology became "hot" when in 1981 IBM introduced its new flagship [[IBM 308X|3081]] mainframe with CPU comprising gate arrays,; they were used in a consumer product, the ZX81; and new entrants to the market increased visibility and credibility.
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Other British companies developed products for gate array design and fabrication. Qudos Limited, a spin-off from Cambridge University, offered a chip design product called Quickchip available for VAX and MicroVAX II systems and as a complete $11,000 turnkey solution, providing a suite of tools broadly similar to those of Ferranti's products including automatic layout, routing, rule checking and simulation functionality for the design of gate arrays. Qudos employed electron beam lithography,<ref name="electronicbusiness19861015_trends">{{ cite magazine | url=https://archive.org/details/sim_electronic-business_1986-10-15_12_20/page/46/mode/1up | title=An emerging market for British engineering tools | magazine=Electronic Business | date=15 October 1986 | access-date=2 March 2022 | last1=Coffey | first1=Margaret | pages=46,48 }}</ref> etching designs onto Ferranti ULA devices that formed the physical basis of these custom chips. Typical prototype production costs were stated as £100 per chip.<ref name="acornuser198604_qudos">{{ cite news | url=https://archive.org/details/AcornUser045-Apr86/page/n16/mode/1up | title=Universities choose chip design on Beeb | work=Acorn User | date=April 1986 | accessdate=10 October 2020 | pages=15 }}</ref> Quickchip was subsequently ported to the [[Acorn Cambridge Workstation]], with a low-end version for the [[BBC Micro]],<ref name="acornuser198609_qudos">{{ cite news | url=https://archive.org/details/AcornUser050-Sep86/page/n8/mode/1up | title=News in brief | work=Acorn User | date=September 1986 | accessdate=10 October 2020 | pages=7 }}</ref> and to the [[Acorn Archimedes]].<ref name="acorn_app155">{{ cite book | url=http://www.4corn.co.uk/archive/docs/AMPAPP/150/APP155%20(1st%20ed)%20-%20(1988)-opt.pdf | title=Hardware expansion and software applications for the Archimedes system | publisher=Acorn Computers Limited | date=September 1988 | issue=1 | access-date=25 April 2021 | pages=22 }}</ref>
===
While the market boomed, profits for the industry were lacking. Semiconductors underwent a series of rolling [[List of recessions in the United States|recessions]] during the 1980s that created a boom-bust cycle. The 1980 and 1981-1982 general recessions were followed by high interest rates that curbed capital spending. This reduction played havoc on the semiconductor business that at the time was highly dependent on capital spending. Manufacturers desperate to keep their fab plants full and afford constant modernization in a fast moving industry became hyper-competitive. The many new entrants to the market drove gate array prices down to the marginal costs of the silicon manufacturers. Fabless companies such as LSI Logic and CDI survived on selling design services and computer time rather than on the production revenues.<ref name=":1" />▼
Indirect competition arose with the development of the [[field-programmable gate array]] (FPGA). [[Xilinx]] was founded in 1984 and its first products were much like early gate arrays, slow and expensive, fit only for some niche markets. However, [[Moore's law|Moore's Law]] quickly made them a force and by the early 1990s were seriously disrupting the gate array market.
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Designers still wished for a way to create their own complex chips without the expense of full-custom design, and eventually this wish was granted with the arrival of not only the FPGA, but [[complex programmable logic device]] (CPLD), metal configurable standard cells (MCSC), and structured ASICs. Whereas a gate array required a back end semiconductor wafer foundry to deposit and etch the interconnections, the FPGA and CPLD had user programmable interconnections. Today's approach is to make the prototypes by FPGAs, as the risk is low and the functionality can be verified quickly. For smaller devices, production cost are sufficiently low. But for large FPGAs, production is very expensive, power hungry, and in many cases do not reach the required speed. To address these issues, several ASIC companies like BaySand, Faraday, Gigoptics and others offer FPGA to ASIC conversion services.
=== Decline ===
▲While the market boomed, profits for the industry were lacking. Semiconductors underwent a series of rolling [[List of recessions in the United States|recessions]] during the 1980s that created a boom-bust cycle. The 1980 and 1981-1982 general recessions were followed by high interest rates that curbed capital spending. This reduction played havoc on the semiconductor business that at the time was highly dependent on capital spending. Manufacturers desperate to keep their fab plants full and afford constant modernization in a fast moving industry became hyper-competitive. The many new entrants to the market drove gate array prices down to the marginal costs of the silicon manufacturers. Fabless companies such as LSI Logic and CDI survived on selling design services and computer time rather than on the production revenues.<ref name=":1" />
As of the early 21st century, the gate array market was a remnant of its former self, driven by the FPGA conversions done for cost or performance reasons. IMI moved out of gate arrays into mixed signal circuits and was later acquired by Cypress Semiconductor in 2001; CDI closed its doors in 1989; and LSI Logic abandoned the market in favor of standard products and was eventually acquired by Broadcom.<ref>{{Cite web|url=http://www.computerhistory.org/siliconengine/companies/|title=Companies|website=The Silicon Engine|publisher=Computer History Museum|access-date=2018-01-28}}</ref>
==
▲A gate array is a prefabricated silicon chip with most [[transistor]]s having no predetermined function. These transistors can be connected by metal layers to form standard [[Negated AND gate|NAND]] or [[NOR gate|NOR]] [[logic gate]]s. These logic gates can then be further interconnected into a complete circuit on the same or later metal layers. Creation of a circuit with a specified function is accomplished by adding this final layer or layers of metal interconnects to the chip late in the manufacturing process, allowing the function of the chip to be customized as desired. These layers are analogous to the copper layers of a [[printed circuit board]].
▲The earliest gate arrays comprised [[bipolar transistors]], usually configured as high performance [[transistor–transistor logic]], [[emitter-coupled logic]] or [[current-mode logic]] logic configurations. [[CMOS]] (complementary [[metal-oxide-semiconductor]]) gate arrays were later developed and came to dominate the industry.
▲Gate array master slices with unfinished chips arrayed across a [[wafer (electronics)|wafer]] are usually prefabricated and stockpiled in large quantities regardless of customer orders. The design and fabrication according to the individual customer specifications can be finished in a shorter time than [[standard cell]] or [[full custom]] design. The gate array approach reduces the non recurring engineering [[Photomask|mask]] costs as fewer custom masks need to be produced. In addition, manufacturing test tooling lead time and costs are reduced - the same test fixtures can be used for all gate array products manufactured on the same [[Die (integrated circuit)|die]] size. Gate arrays were the predecessor of the more complex [[Structured ASIC platform|structured ASIC]]; unlike gate arrays, structured ASICs tend to include predefined or configurable memories and/or analog blocks.
▲An application circuit must be built on a gate array that has enough gates, wiring and I/O pins. Since requirements vary, gate arrays usually come in families, with larger members having more of all resources, but correspondingly more expensive. While the designer can fairly easily count how many gates and I/Os pins are needed, the number of routing tracks needed may vary considerably even among designs with the same amount of logic. (For example, a [[crossbar switch]] requires much more routing than a [[systolic array]] with the same gate count.) Since unused routing tracks increase the cost (and decrease the performance) of the part without providing any benefit, gate array manufacturers try to provide just enough tracks so that most designs that will fit in terms of gates and I/O pins can be routed. This is determined by estimates such as those derived from [[Rent's rule]] or by experiments with existing designs.
▲The main drawbacks of gate arrays are their somewhat lower density and performance compared with other approaches to ASIC design. However this style is often a viable approach for low production volumes.
== Uses ==
{{expand section}}
Gate arrays were used widely in the [[home computer]] market in the United Kingdom in the early 1980s, including in the [[Sinclair ZX81]] and [[Sinclair Spectrum]], the [[BBC Micro]] and [[Acorn Electron]], and the [[Commodore Amiga]].
== References ==▼
{{refs}}
== External links ==▼
▲==References==
* {{Commons category-inline|Gate arrays}}▼
▲==External links==
▲*{{Commons category-inline|Gate arrays}}
[[Category:Gate arrays| ]]
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