No instruction set computing: Difference between revisions

Revision as of 02:04, 30 June 2022

Revision as of 20:41, 8 July 2022

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== Overview ==

NISC is a statically- scheduled horizontal nanocoded architecture (SSHNA). The term "statically scheduled" means that the [[operation scheduling]] and [[hazard handling]] are done by a [[compiler]]. The term "horizontal nanocoded" means that NISC does not have any predefined [[instruction set]] or [[microcode]]. The compiler generates nanocodes which directly control [[functional unit]]s, [[Processor register|register]]s and [[multiplexer]]s of a given [[datapath]]. Giving low-level control to the compiler enables better utilization of datapath resources, which ultimately result in better performance. The benefits of NISC technology are:

* Simpler controller: no hardware scheduler, no instruction decoder

* Better performance: more flexible architecture, better resource utilization

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==Zero instruction set computer==

In [[computer science]], '''zero instruction set computer''' ('''ZISC''') refers to a [[computer architecture]] based solely on [[pattern matching]] and absence of [[instruction (computer science)|(micro-)instructions]] in the classical{{huhclarify|reason=What would be an example of a non-classical micro-instruction?|date=December 2016}}<!-- some confusion here could probably be resolved by updating the instruction article --> sense. These chips are known for being thought of as comparable to the [[neural network]]s, being marketed for the number of "synapses" and "neurons".<ref name="BrainChip"/> The [[acronym and initialism|acronym]] ZISC alludes to [[reduced instruction set computer]] (RISC).{{factcitation needed|date=December 2016}}

ZISC is a hardware implementation of [[Kohonen network]]s (artificial neural networks) allowing massively parallel processing of very simple data (0 or 1). This hardware implementation was invented by Guy Paillet<ref name="Neuron circuit">{{Cite web|url=https://patents.google.com/patent/US5621863|title = Neuron circuit}}</ref> and Pascal Tannhof (IBM),<ref>{{cite web |url=https://www.researchgate.net/profile/Pascal-Tannhof |title=Profile: Pascal Tannhof |website=[[ResearchGate]]}}</ref><ref>{{Cite web|urlname=https://patents.google.com/patent/US5621863|title = "Neuron circuit}}<"/ref> developed in cooperation with the IBM chip factory of [[Essonnes]], in France, and was commercialized by IBM.

The ZISC architecture alleviates the [[memory bottleneck]]{{clarify|date=December 2016}} by blending pattern memory with pattern learning and recognition logic.{{how|date=December 2016}} Their massively parallel computing solves the {{Clarify|text="[[Winner-take-all in action selection|winner takes all problem in action selection]]"|post-text=from [[Winner-take-all (computing)|Winner-takes-all]] problem in [[Artificial neural network|Neural Network]]s|reason=Per [https://web.archive.org/web/20170101001452/https://pdfs.semanticscholar.org/1e0c/54bd88223e009997a04dcd2a0f3fa0af3848.pdf source], [[Winner-take-all (computing)|Winner-takes-all]] is defined as a different principle from [[Winner-take-all in action selection]], but both are relevant to [[Artificial neural network|Neural Network]]s|date=December 2016}} by allotting each "neuron" its own memory and allowing simultaneous problem-solving the results of which are settled up disputing with each other.<ref name="Gigaom"/>

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* [http://www.lsmarketing.com/LSMFiles/9809-ai1.htm From CISC to RISC to ZISC] by S. Liebman on lsmarketing.com

* [https://web.archive.org/web/20060527023259/http://www.aboutai.net/DesktopDefault.aspx?article=aa071800a.htm&tabid=2 Neural Networks on Silicon] at aboutAI.net

* {{dmozcurlie|Computers/Hardware/Components/Processors/ZISC}}

* [https://patentscope.wipo.int/search/zh/detail.jsf;jsessionid=2EEDB543070890EAD531331F04F3C2DB.wapp2nB?docId=FR290835374&_cid=P21-K8UX94-10474-3 French Patent Request] NISC for purely applicative engine - the sole operation of application (no lambda-calculus that is a particular case of quasi-applicative systems with two operations : application and abstraction - Curry 1958 p.&nbsp;31)

{{CPU technologies}}