NISC is a statically scheduled horizontal nanocoded architecture (SSHNA). The term "statically scheduled" means that the [[Scheduling (computing)|operation scheduling]] and handiling [[hazardHazard (computer handlingarchitecture)|Hazards]] are done by a [[compiler]]. The term "horizontal nanocoded" means that NISC does not have any predefined [[instruction set]] or [[microcode]]. The compiler generates nanocodes which directly control [[functional unit]]s, [[Processor register|register]]s and [[multiplexer]]s of a given [[datapath]]. Giving low-level control to the compiler enables better utilization of datapath resources, which ultimately result in better performance. The benefits of NISC technology are:
* Simpler controller: no hardware scheduler, no instruction decoder
* Better performance: more flexible architecture, better resource utilization
