Memory segmentation: Difference between revisions

Revision as of 19:47, 11 July 2022

Revision as of 20:30, 12 July 2022

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{{about|segmented computer memory|segments in object code|Object file}}

{{use dmy dates|date=July 2022|cs1-dates=y}}

'''Memory segmentation''' is an [[operating system]] [[memory management (operating systems)|memory management]] technique of division of a [[computer]]'s [[primary memory]] into '''segments''' or '''sections'''. In a [[Computer architecture|computer system]] using segmentation, a reference to a memory ___location includes a value that identifies a segment and an [[offset (computer science)|offset]] (memory ___location) within that segment. Segments or sections are also used in [[object file]]s of compiled programs when they are [[Linker (computing)|linked]] together into a [[program image]] and when the image is [[Loader (computing)|loaded]] into memory.

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Segments may be created for program [[module (programming)|module]]s, or for classes of memory usage such as [[Code segment|code]] and [[data segment]]s.<ref name="glaser1965"/> Certain segments may be shared between programs.<ref name="holt1961"/><ref name="englander" />

Segmentation was originally invented as a method by which [[system software]] could isolate software [[Process (computing)|processes]] ([[Task (computing)|tasks]]) and data they are using. It was intended to increase reliability of the systems running multiple processes simultaneously.<ref name=":0">{{Cite book|url=https://www.amd.com/system/files/TechDocs/24593.pdf|title=AMD64 Technology AMD64 Architecture Programmer's Manual Volume 2: System Programming|publisher=Advanced Micro Devices|yeardate=2018|volume=2|pages=5|language=en|chapter=1.2 Memory Management}}</ref> In a [[X86-64|x86-64 architecture]] it is considered legacy and most x86-64-based modern system software don't use memory segmentation. Instead they handle programs and their data by utilizing [[Paging|memory-paging]] which also serves as a way of memory protection. However most x86-64 implementations still support it for backward compatibility reasons.<ref name=":0" />

==Hardware implementation==

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In this case each segment has an associated flag indicating whether it is present in main memory or not. If a segment is accessed that is not present in main memory, an exception is raised, and the [[operating system]] will read the segment into memory from secondary storage.

Segmentation is one method of implementing [[memory protection]].<ref name="ostep-1">{{cite book|title=Operating Systems: Three Easy Pieces|chapter=Segmentation|chapter-url=http://pages.cs.wisc.edu/~remzi/OSTEP/vm-segmentation.pdf|publisher= Arpaci-Dusseau Books|yeardate = 2014|first1 = Remzi H.|last1 =Arpaci-Dusseau|first2=Andrea C.|last2 = Arpaci-Dusseau}}</ref> [[Page (computer memory)|Paging]]<!-- please, do not "simplify" or "fix" the link. The [[paging]] article is about a virtual memory technique, not about memory protection --> is another, and they can be combined. The size of a memory segment is generally not fixed and may be as small as a single [[byte]].<ref>{{cite book|publisher=Intel Corporation|title=Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3 (3A, 3B & 3C): System Programming Guide|yeardate=2012|pages=3–13|url=http://download.intel.com/products/processor/manual/325384.pdf}}</ref>

Segmentation has been implemented several ways on various hardware, with or without paging. Intel [[x86 memory segmentation]] does not fit either model and is discussed separately below, and also in greater detail in a separate article.

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==History==

The [[Burroughs Corporation]] [[Burroughs large systems|B5000]] computer was one of the first to implement segmentation, and "perhaps the first commercial computer to provide virtual memory"<ref>{{cite web|last=Mayer|first=Alastair J. W.|title=The Architecture of the Burroughs B5000 - 20 Years Later and Still Ahead of the Times?|url=http://www.smecc.org/The%20Architecture%20%20of%20the%20Burroughs%20B-5000.htm|access-date=March 15, 2012-03-15}}</ref> based on segmentation. The later [[Burroughs large systems#B6500|B6500]] computer also implemented segmentation; a version of its architecture is still in use today on the Unisys ClearPath Libra servers.

The [[GE-600 series|GE-645]] computer, a modification of the GE-635 with segmentation and paging support added, was designed in 1964 to support [[Multics]].

The [[Intel iAPX 432]],<ref>{{cite book|publisher=Intel Corporation|title=Introduction to the IAPX 432 Architecture|yeardate=1981|pages=78|url=http://bitsavers.org/components/intel/iAPX_432/171821-001_Introduction_to_the_iAPX_432_Architecture_Aug81.pdf}}</ref> begun in 1975, attempted to implement a true segmented architecture with memory protection on a microprocessor.

The 960MX version of the [[Intel i960]] processors supported load and store instructions with the source or destination being an "access descriptor" for an object, and an offset into the object, with the access descriptor being in a 32-bit register and with the offset computed from a base offset in the next register and from an additional offset and, optionally, an index register specified in the instruction. An access descriptor contains permission bits and a 26-bit object index; the object index is an index into a table of object descriptors, giving an object type, an object length, and a physical address for the object's data, a page table for the object, or the top-level page table for a two-level page table for the object, depending on the object type.<ref>{{cite book|url=http://bitsavers.org/pdf/biin/BiiN_CPU_Architecture_Reference_Man_Jul88.pdf|title=BiiN CPU Architecture Reference Manual|date=July 1998|publisher=BiiN}}</ref>

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==Examples==

===S/370 architecture===

In the [[IBM System/370]] models{{efn|Models 115, 125, 135, 138, 145, 148, 155 II, 158, 165 II and 168}} with virtual storage<ref name="S370">{{cite manual

| title = IBM System/370 Principles of Operation

| id = GA22-7000-4

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}}

<!-- This is the most recent version that I could find in bitsavers -->

</ref><ref name="S370-10">{{cite manual

| title = IBM System/370 Principles of Operation

| id = GA22-7000-10

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Each of IBM's DAT implementations includes a translation cache, which IBM called a Translation Lookaside Buffer (TLB). While Principles of Operation discusses the TLB in general terms, the details are not part of the architecture and vary from model to model.

Starting with the [[IBM 303X|3031, 3032 and 3033]] processor complexes, IBM offered a feature called ''Dual-address Space''<ref name="S370-10"/>{{rp|at=Dual-Address-Space Control|pp=5-13-5-17}}{{rp|at=DAS Authorization Mechanisms|pp=5-17-5-20}}{{rp|at=PC-Number Translation|pp=5-21-5-24}}<ref name="S370-XA">{{cite manual

| title = IBM System/370 Extended Architecture Principles of Operation

| id = SA22-7085-1

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The [[Intel 80386]] and later processors also support paging; in those processors, the segment table, rather than pointing to a page table for the segment, contains the segment address in ''linear memory''. Addresses in linear memory are then mapped to physical addresses using a separate page table, if paging is enabled.

The [[x86-64]] architecture does not use segmentation in long mode (64-bit mode).<ref name=":1">{{Cite book|url=https://www.amd.com/system/files/TechDocs/24594.pdf|title=AMD64 Technology AMD64 Architecture Programmer's Manual Volume 2: System Programming|publisher=Advanced Micro Devices|yeardate=2018|volume=2|language=en}}</ref> In a [[X86-64|x86-64 architecture]] it is considered legacy and most x86-64-based modern system software don't use memory segmentation. Instead they handle programs and their data by utilizing [[Paging|memory-paging]] which also serves as a way of memory protection. Though most x86-64 implementations still support it for backward compatibility reasons.<ref name=":0" /> Four of the segment registers: CS, SS, DS, and ES are forced to 0, and the limit to 2⁶⁴. The segment registers FS and GS can still have a nonzero base address. This allows operating systems to use these segments for special purposes.

== See also ==

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* [[Flat memory model]]

== Notes ==

{{notelist}}

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<ref name="holt1961">{{cite journal

|title=Program Organization and Record Keeping for Dynamic Storage Allocation

|first=A.Anatol W.

|last=Holt

|yeardate=1961

|journal=Communications of the ACM

|volume=4

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|title=System Design of a Computer for Time Sharing Applications

|url=https://multicians.org/fjcc2.html

|first1=E.Edward L.

|last1=Glaser

|first2=J.John F.

|last2=Couleur

|first3=G. A.

|last3=Oliver

|yeardate=1965

|conference=1965 Fall Joint Computer Conference}}

</ref>

<ref name="englander">{{cite book

|last=Englander |first=Irv |yeardate=2003

|title=The architecture of computer hardware and systems software |edition=3rd

|publisher=Wiley |isbn=0-471-07325-3