Content deleted Content added
Guy Harris (talk | contribs) →Intro and definition: Comer's book speaks more of traditional microcoded processors than anything like modern x86 processors. |
Guy Harris (talk | contribs) →Intro and definition: And the P6. |
||
Line 332:
::::Section 8.9 "Microcoded Instructions" is discussing a traditional microcoded processor. Section 8.10 "Microcode Variations" says that "“On some CPUs, microcode implements the entire fetch-execute cycle — the microcode interprets the opcode, fetches operands, and performs the specified operation.", which is what I referred to as a "fully-microcoded processor", and which also implies that there are alternatives, such as "hardware directly fetches and decodes instructions and fetches some or all operands, and then jumps to microcode to implement the instruction".
::::Unfortunately, the book doesn't cover the way most general-purpose processors work these days; the word "superscalar" appears nowhere in the book, according to the Books app, and "out-of-order" only appears in one section with one paragraph. The stuff that processors from smartphones to supercomputers do is in sections 8.19 through 8.21, with very little detail. [[User:Guy Harris|Guy Harris]] ([[User talk:Guy Harris|talk]]) 09:19, 20 July 2022 (UTC)
:::::As for micro-operations in the P6-and-later sense, the [[P6 (microarchitecture)]] page says:
:::::{{quote|P6 processors dynamically translate [[IA-32]] instructions into sequences of buffered RISC-like [[micro-operation]]s, then analyze and reorder the micro-operations to detect parallelizable operations that may be issued to more than one [[execution unit]] at once.<ref>{{cite journal |last1=Gwennap |first1=Linley |title=Intel's P6 Uses Decoupled Scalar Design |journal=Microprocessor Report |date=16 February 1995 |volume=9 |issue=2 |url=http://www.cs.cmu.edu/afs/cs.cmu.edu/academic/class/15213-f01/docs/mpr-p6.pdf}}</ref> The Pentium Pro was the first x86 microprocessor designed by Intel to use this technique, though the NexGen [[Nx586]], introduced in 1994, did so earlier.}}
:::::The reference says that
:::::{{quote|The decoders translate x86 instructions into uops. P6 uops have a fixed length of 118 bits, using a regular structure to encode an operation, two sources, and a destination. The source and destination fields are each wide enough to contain a 32-bit operand. Like RISC instructions, uops use a load/store model; x86 instructions that operate on memory must be broken into a load uop, an ALU uop, and possibly a store uop.}}
:::::which is a description of a "generate micro-operations on the fly" processor, not a traditional "microcode as instruction set simulator" processor. [[User:Guy Harris|Guy Harris]] ([[User talk:Guy Harris|talk]]) 09:29, 20 July 2022 (UTC)
| |||