FIFO (computing and electronics): Difference between revisions

Revision as of 14:15, 21 July 2022

Revision as of 09:12, 25 July 2022

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=== Status flags ===

Examples of FIFO status flags include: full, empty, almost full, and almost empty. A FIFO is empty when the read [[address register]] reaches the write address register. A FIFO is full when the write address register reaches the read 0addressaddress register. Read and write addresses are initially both at the first memory ___location and the FIFO queue is ''empty''.

In both cases, the read and write addresses end up being equal. To distinguish between the two situations, a simple and robust solution is to add one extra [[bit]] for each read and write address which is inverted each time the address wraps. With this set up, the disambiguation conditions are:

* When the read address register equals the write address register, the FIFO is empty.

* When the read addressand [[Bitwrite numbering#Leastaddress significantregisters bit|leastdiffer significantonly bit]] (LSB) equals the write address LSBs andin the extra [[Bit numbering#Most significant bit|most significant bit]] and the rest are differentequal, the FIFO is full.

== See also ==