Flow to HDL: Difference between revisions

Revision as of 15:23, 22 February 2007

Revision as of 15:25, 22 February 2007

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This page is to describe tools and methods that convert Flow based system design into hardware description languages like [[VHDL]] or [[Verilog]]. Typically this is a method of creating designs for [[Field-programmable_gate_array]], [[ASIC]] prototyping and [[DSP]] design. Flow based system design is well suited to [[Field-programmable_gate_array |FPGA]] design as it's easier to specify the inateinnate parreleismparallelism of the architecture.

== Discussion ==

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== Examples ==

*Xilinx System Generator from [http://www.Xilinx.com/ Xilinx]

*StarBridge VIVA from [http://www.starbridgesystems.com/ StarBridge Systems]

== External links ==