Cache placement policies: Difference between revisions

Revision as of 06:08, 30 August 2022

Revision as of 04:25, 12 September 2022

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== Direct-mapped cache ==

In a direct-mapped cache structure, the cache is organized into multiple sets<ref name=":0" /> with a single cache line per set. Based on the address of the memory block, it can only occupy a single cache line. The cache can be framed as a ({{math| ''n*'' × 1)}} column matrix.<ref name=":1">{{Cite book|title=Fundamentals of Parallel Multi-core Architecture|last=Solihin|first=Yan|publisher=Taylor & Francis|year=2015|isbn=978-1482211184|pages=136–141}}</ref>

=== To place a block in the cache ===

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== Fully associative cache ==

In a fully associative cache, the cache is organized into a single cache set with multiple cache lines. A memory block can occupy any of the cache lines. The cache organization can be framed as ({{math|1* × ''m)''}} row matrix.<ref name=":1" />

=== To place a block in the cache ===

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Set-associative cache is a trade-off between direct-mapped cache and fully associative cache.

A set-associative cache can be imagined as a ({{math|''n*'' × ''m)''}} matrix. The cache is divided into ‘n’ sets and each set contains ‘m’ cache lines. A memory block is first mapped onto a set and then placed into any cache line of the set.

The range of caches from direct-mapped to fully associative is a continuum of levels of set associativity. (A direct-mapped cache is one-way set-associative and a fully associative cache with ''m'' cache lines is ''m''-way set-associative.)