Bit-serial architecture: Difference between revisions

Revision as of 12:31, 21 October 2022

Revision as of 22:55, 5 November 2022

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{{Short description|Computational system in which data are sent one bit at a time down a wire}}

{{Use dmy dates|date=November 2022|cs1-dates=y}}

{{Use list-defined references|date=November 2022}}

In [[digital logic]] applications, '''bit-serial architectures''' send data one bit at a time, along a single wire, in contrast to [[Parallel transmission|bit-parallel]] [[word (computer architecture)|word]] architectures, in which data values are sent all bits or a word at once along a group of wires.

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Bit-serial architectures were developed for [[digital signal processing]] in the 1960s through 1980s, including efficient structures for bit-serial multiplication and accumulation.<ref name="Denyer_1995"/>

Often, N serial processors will take less [[FPGA]] area and have a higher total performance than a single N-bit parallel processor.<ref name="Andraka"/>

Raymond J. Andraka.

[http://www.fpga-guru.com/files/supercn.pdf "Building a High Performance Bit Serial Processor in an FPGA"].

</ref>

==See also==

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* [[Bit slicing]]

* [[Digit-serial architecture]]<!-- with possibilities -->

* [[BKM algorithm]]

* [[CORDIC algorithm]]

==References==

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<ref name="Denyer_1995">

{{cite book |title=VLSI signal processing: a bit-serial approach |series=VLSI systems series |author-first1=Peter B. |author-last1=Denyer |author-link1=Peter B. Denyer |author-first2=David |author-last2=Renshaw |publisher=[[Addison-Wesley]] |date=1985 |isbn=978-0-201-13306-6 |url=https://books.google.com/books?id=EklTAAAAMAAJ}}</ref>

<ref name="Andraka">{{cite web |title=Building a High Performance Bit Serial Processor in an FPGA |author-first=Raymond J. |author-last=Andraka. |url=http://www.fpga-guru.com/files/supercn.pdf}}</ref>

}}