Application-specific instruction set processor: Difference between revisions

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{{Short description|Processor with an instruction set customized (optimized) for a specific task}}
{{Use American English|date = March 2019}}
{{Use mdy dates|date = March 2019}}
{{More footnotes|date=January 2015}}
An '''application-specific instruction set processor''' ('''ASIP''') is a component used in [[system- on- a- chip]] design. The [[instruction set architecture]] of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose [[central processing unit|CPU]] (CPU) and the performance of an [[application-specific integrated circuit|ASIC]] (ASIC).
 
Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA (instruction-set architecture) and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to a [[field-programmable gate array]] (FPGA) or during the chip synthesis. ASIPs have two ways of generating code: either through a retargetable code generator or through a retargetable compiler generator. The retargetable code generator uses the application, ISA, and Architecture Template to create the code generator for the object code. The retargetable compiler generator uses only the ISA and Architecture Template as the basis for creating the compiler. The application code will then be used by the compiler to create the object code.<ref>{{Cite journal|last1=Jain|first1=M.K.|last2=Balakrishnan|first2=M.|last3=Kumar|first3=A.|date=2001|title=ASIP design methodologies: survey and issues|url=https://ieeexplore.ieee.org/document/902643|journal=VLSI Design 2001. Fourteenth International Conference on VLSI Design|___location=Bangalore, India|publisher=IEEE Comput. Soc|pages=76–81|doi=10.1109/ICVD.2001.902643|isbn=978-0-7695-0831-3|s2cid=14053636 }}</ref>