Latency oriented processor architecture: Difference between revisions

Content deleted Content added
Citation bot (talk | contribs)
Add: isbn. | Use this bot. Report bugs. | Suggested by Whoop whoop pull up | #UCB_webform 13/1195
Line 4:
==Flynn's taxonomy==
{{Main|Flynn's taxonomy}}
LatencyTypically, latency oriented processor architectures wouldexecute normallya fallsingle intotask theoperating categoryon ofa single data stream, and so they are [[Single instruction, single data|SISD]] classification under flynnFlynn's taxonomy. This implies a typical characteristic of latencyLatency oriented processor architectures ismight to execute a single task operating on a single data stream.also Someinclude [[Single instruction, multiple data|SIMD]] styleinstruction multimediaset extensions of popular instruction sets, such as Intel [[MMX (instruction set)|MMX]] and [[Streaming SIMD Extensions|SSE]] instructions, should also fall under the category of latency oriented processor architectures;<ref name=YanSohilin2016/>even because,though althoughthese theyextensions operate on a large data setsets, their primary goal is also to reduce overall latency<ref for the entire task at handname=YanSohilin2016/>.
 
==Implementation techniques==