Depletion-load NMOS logic: Difference between revisions

Revision as of 04:40, 25 November 2022

Revision as of 00:13, 7 December 2022

Line 1:

{{short description|Form of digital logic family in integrated circuits}}

[[File:Nmos depletion and.svg|right|thumb|A depletion-load nMOSNMOS [[NAND gate]]]]

In [[integrated circuit]]s, '''depletion-load NMOS''' is a form of digital [[logic family]] that uses only a single power supply voltage, unlike earlier [[NMOS logic|NMOS]] (n-type [[metal-oxide semiconductor]]) logic families that needed more than one different power supply voltage. Although manufacturing these integrated circuits required additional processing steps, improved switching speed and the elimination of the extra power supply made this logic family the preferred choice for many [[microprocessor]]s and other logic elements.

[[Depletion and enhancement modes|Depletion-mode]] n-type [[MOSFET]]s as load transistors allow single voltage operation and achieve greater speed than possible with pure enhancement-load devices. This is partly because the depletion-mode MOSFETs can be a better [[current source]] approximation than the simpler enhancement-mode transistor can, especially when no extra voltage is available (one of the reasons early pMOSPMOS and nMOSNMOS chips demanded several voltages).

The inclusion of depletion-mode n-MOSNMOS transistors in the [[semiconductor manufacturing|manufacturing process]] demanded additional manufacturing steps compared to the simpler enhancement-load circuits; this is because depletion-load devices are formed by increasing the amount of [[dopant]] in the load transistors channel region, in order to adjust their [[threshold voltage]]. This is normally performed using [[ion implantation]].

Although the [[CMOS]] process replaced most NMOS designs during the 1980s, some depletion-load nMOSNMOS designs are still produced, typically in parallel with newer CMOS counterparts. One example of this is the [[Z80|Z84015]]<ref>''See http://www.zilog.com/index.php?option=com_product&Itemid=26&mode=showProductDetails&familyId=20&productId=Z84015''.</ref> and Z84C15.<ref>''See http://www.zilog.com/index.php?option=com_product&Itemid=26&mode=showProductDetails&familyId=20&productId=Z84C15''.</ref>

==History and background==

Line 20:

In the late 1960s, [[bipolar junction transistor]]s were faster than (p-channel) MOS transistors then used and were more reliable, but they also consumed much more power, required more area, and demanded a more complicated manufacturing process. MOS ICs were considered interesting but inadequate for supplanting the fast bipolar circuits in anything but niche markets, such as low power applications. One of the reasons for the low speed was that MOS transistors had [[Gate (transistor)|gates]] made of [[aluminum]] which led to considerable [[parasitic capacitance]]s using the manufacturing processes of the time. The introduction of transistors with gates of [[polycrystalline silicon]] (that became the ''de facto'' standard from the mid-1970s to early 2000s) was an important first step in order to reduce this handicap. This new [[self-aligned gate|''self-aligned silicon-gate'']] transistor was introduced by [[Federico Faggin]] at [[Fairchild Semiconductor]] in early 1968; it was a refinement (and the first working implementation) of ideas and work by John C. Sarace, Tom Klein and [[Robert W. Bower]] (around 1966–67) for a transistor with lower parasitic capacitances that could be manufactured as part of an IC (and not only as a [[discrete component]]). This new type of pMOS transistor was 3–5 times as fast (per watt) as the aluminum-gate pMOS transistor, and it needed less area, had much lower leakage and higher reliability. The same year, Faggin also built the first IC using the new transistor type, the ''Fairchild 3708'' (8-bit [[analogue electronics|analog]] [[multiplexer]] with [[Binary decoder|decoder]]), which demonstrated a substantially improved performance over its metal-gate counterpart. In less than 10 years, the silicon gate MOS transistor replaced bipolar circuits as the main vehicle for complex digital ICs.

===nMOSNMOS and back-gate bias===

There are a couple of drawbacks associated with pMOSPMOS: The [[electron hole]]s that are the charge (current) carriers in pMOSPMOS transistors have lower mobility than the [[electron]]s that are the charge carriers in nMOSNMOS transistors (a ratio of approximately 2.5), furthermore pMOSPMOS circuits do not interface easily with low voltage positive logic such as [[Diode–transistor logic|DTL-logic]] and [[Transistor–transistor logic|TTL-logic]] (the 7400-series). However, pMOSPMOS transistors are relatively easy to make and were therefore developed first — ionic contamination of the gate oxide from [[Etching (microfabrication)|etching chemical]]s and other sources can very easily prevent (the [[electron]] based) nMOSNMOS transistors from switching off, while the effect in (the [[electron-hole]] based) pMOSPMOS transistors is much less severe. Fabrication of nMOSNMOS transistors therefore has to be many times cleaner than bipolar processing in order to produce working devices.

Early work on nMOSNMOS integrated circuit (IC) technology was presented in a brief [[IBM]] paper at [[ISSCC]] in 1969. [[Hewlett-Packard]] then started to develop nMOSNMOS IC technology to get the promising speed and easy interfacing for its calculator business.<ref>These calculators (like the [[Datapoint 2200]] and others) were in many ways small [[desktop computer]]s, but preceded the [[Apple II]] and the [[IBM PC]] by many years.</ref> Tom Haswell at HP eventually solved many problems by using purer raw materials (especially aluminum for interconnects) and by adding a bias voltage to make the [[threshold voltage|gate threshold]] large enough; this ''back-gate bias'' remained a ''de facto'' standard solution to (mainly) [[sodium]] contaminants in the gates until the development of [[ion implantation]] (see below). Already by 1970, HP was making good enough nMOS ICs and had characterized it enough so that Dave Maitland was able to write an article about nMOS in the December, 1970 issue of Electronics magazine. However, nMOSNMOS remained uncommon in the rest of the semiconductor industry until 1973.<ref>''Shown by its mere mention in a large roundup article written by GE engineer Herman Schmid that appeared in the December, 1972 issue of IEEE Transactions on Manufacturing Technology. Although it cites Maitland’s 1970 article in Electronics, Schmid’s article does not discuss nMOSNMOS fabrication in detail but it does cover pMOSPMOS and even CMOS fabrication extensively.''</ref>

The production-ready nMOSNMOS process enabled HP to develop the industry’s first 4-kbit IC [[Read-only memory|ROM]]. [[Motorola]] eventually served as a second source for these products and so became one of the first commercial semiconductor vendors to master the nMOSNMOS process, thanks to Hewlett-Packard. A while later, the startup company [[Intel]] announced a 1-kbit pMOS DRAM, called ''1102'', developed as a custom product for [[Honeywell]] (an attempt to replace magnetic [[core memory]] in their [[mainframe computer]]s). HP’s calculator engineers, who wanted a similar but more robust product for the [[HP 9800 series|9800 series]] calculators, contributed IC fabrication experience from their 4-kbit ROM project to help improve Intel DRAM’s reliability, operating-voltage, and temperature range. These efforts contributed to the heavily enhanced ''Intel 1103'' 1-kbit pMOS DRAM, which was the world’s first commercially available [[DRAM]] IC. It was formally introduced in October 1970, and became Intel’s first really successful product.<ref>{{cite web|url=http://www.hp9825.com/html/prologues.html |title=Prologues |publisher=Hp9825.com |date= |accessdate=2022-03-15}}</ref>

===Depletion-mode transistors===

Line 32:

Early MOS logic had one transistor type, which is [[enhancement mode]] so that it can act as a logic switch. Since suitable resistors were hard to make, the logic gates used saturated loads; that is, to make the one type of transistor act as a load resistor, the transistor had to be turned always on by tying its gate to the power supply (the more negative rail for [[PMOS logic]], or the more positive rail for [[NMOS logic]]). Since the current in a device connected that way goes as the square of the voltage across the load, it provides poor pullup speed relative to its power consumption when pulled down. A resistor (with the current simply proportional to the voltage) would be better, and a current source (with the current fixed, independent of voltage) better yet. A [[depletion-mode]] device with gate tied to the opposite supply rail is a much better load than an enhancement-mode device, acting somewhere between a resistor and a current source.

The first depletion-load nMOSNMOS circuits were pioneered and made by the [[DRAM]] manufacturer [[Mostek]], which made depletion-mode transistors available for the design of the original [[Zilog Z80]] in 1975–76.<ref>''Zilog relied on [[Mostek]] and [[Synertek]] to produce the Z80 and other chips before their own production facilities were ready.''</ref> Mostek had the [[ion implantation]] equipment needed to create a [[doping (semiconductor)|doping profile]] more precise than possible with [[diffusion]] methods, so that the [[threshold voltage]] of the load transistors could be adjusted reliably. At Intel, depletion load was introduced in 1974 by Federico Faggin, an ex-Fairchild engineer and later the founder of [[Zilog]]. Depletion-load was first employed for a redesign of one of Intel's most important products at the time, a +5V-only 1Kbit nMOSNMOS [[Static random-access memory|SRAM]] called the ''2102'' (using more than 6000 transistors<ref>''Each bit demands six transistors in a typical [[static RAM]].''</ref>). The result of this redesign was the significantly faster ''2102A'', where the highest performing versions of the chip had access times of less than 100ns, taking MOS memories close to the speed of bipolar RAMs for the first time.<ref>''See for instance: http://www.intel4004.com/sgate.htm or http://archive.computerhistory.org/resources/text/Oral_History/Faggin_Federico/Faggin_Federico_1_2_3.oral_history.2004.102658025.pdf'' {{Webarchive|url=https://web.archive.org/web/20170110232713/http://archive.computerhistory.org/resources/text/Oral_History/Faggin_Federico/Faggin_Federico_1_2_3.oral_history.2004.102658025.pdf |date=2017-01-10 }}</ref>

Depletion-load nMOSNMOS processes were also used by several other manufacturers to produce many incarnations of popular 8-bit, 16-bit, and 32-bit CPUs. Similarly to early pMOSPMOS and nMOSNMOS CPU designs using [[Channel (transistor)|enhancement mode]] MOSFETs as loads, depletion-load nMOS designs typically employed various types of [[dynamic logic (digital logic)|dynamic logic]] (rather than just static gates) or [[Pass transistor logic|pass transistor]]s used as dynamic [[latch (electronics)|clocked latch]]es. These techniques can enhance the area-economy considerably although the effect on the speed is complex. Processors built with depletion-load nMOSNMOS circuitry include the [[Motorola 6800|6800]] (in later versions<ref name = "M6800 redesign">{{Cite journal| title = Motorola Redesigns 6800 | journal = Microcomputer Digest | volume = 3 | issue = 2 | page =4 | publisher = Microcomputer Associates | ___location = Santa Clara, CA | date = August 1976 | url = http://www.bitsavers.org/pdf/microcomputerAssociates/Microcomputer_Digest_v03n02_Aug76.pdf}} "Motorola is redesigning the M6800 microprocessor family by adding depletion loads to increase speed and reduce the 6800 CPU size to 160 mils."</ref>), the [[6502]], [[Signetics 2650]], [[8085]], [[6809]], [[8086]], [[Z8000]], [[NS32016]], and many others (whether or not the HMOS processors below are included, as special cases).

A large number of support and peripheral ICs were also implemented using (often static) depletion-load based circuitry. However,

there were never any standardized [[logic family|logic families]] in nMOSNMOS, such as the [[transistor-transistor logic|bipolar]] [[7400 series]] and the [[CMOS]] [[4000 series]], although designs with several second source manufacturers often achieved something of a de facto standard component status. One example of this is the nMOSNMOS [[Intel 8255|8255 PIO]] design, originally intended as an 8085 peripheral chip, that has been used in Z80 and x86 [[embedded system]]s and many other contexts for several decades. Modern low power versions are available as CMOS or BiCMOS implementations, similar to the 7400-series.

===Intel HMOS===

Intel's own depletion-load NMOS process was known as '''HMOS''', for ''High density, short channel MOS''. The first version was introduced in late 1976 and first used for their [[static RAM]] products,<ref>{{cite journal |first1=A.M. |last1=Volk |first2=P.A. |last2=Stoll |first3=P. |last3=Metrovich |title=Recollections of Early Chip Development at Intel |journal=Intel Technology Journal |volume=5 |issue=Q1 |pages= |date=2001 |url=https://www.intel.com/content/dam/www/public/us/en/documents/research/2001-vol05-iss-1-intel-technology-journal.pdf}}</ref> it was soon being used for faster and/or less power hungry versions of the 8085, 8086, and other chips.

HMOS continued to be improved and went through four distinct generations. According to Intel, HMOS II (1979) provided twice the density and four times the speed/power product over other typical contemporary depletion-load nMOSNMOS processes.<ref>See for instance: {{cite book |first=Leo J. |last=Scanlon |first2=C.W. |last2=Moody |title=The 68000 Principles and programming |publisher=H.W. Sams |date=1981 |isbn=978-0-672-21853-8 |oclc=7802969}}</ref> This version was widely licensed by 3rd parties, including (among others) [[Motorola]] who used it for their [[Motorola 68000]], and [[Commodore Semiconductor Group]], who used it for their [[MOS Technology 8502]] die-shrunk [[MOS 6502]].

The original HMOS process, later referred to as HMOS I, had a channel length of 3 microns, which was reduced to 2 for the HMOS II, and 1.5 for HMOS III. By the time HMOS III was introduced in 1982, Intel had begun a switch to their [[CHMOS]] process, a [[CMOS]] process using design elements of the HMOS lines. One final version of the system was released, HMOS-IV. A significant advantage to the HMOS line was that each generation was deliberately designed to allow existing layouts to die-shrink with no major changes. Various techniques were introduced to ensure the systems worked as the layout changed.<ref>{{cite conference |conference=ISSCC 82 |date=1982 |title=HMOS III Technology}}</ref><ref>{{cite journal |first1=G.E. |last1=Atwood |first2=H. |last2=Dun |first3=J. |last3=Langston |first4=E. |last4=Hazani |first5=E.Y. |last5=So |first6=S. |last6=Sachdev |first7=K. |last7=Fuchs |title=HMOS III technology |journal=IEEE Journal of Solid-State Circuits |volume=17 |issue=5 |pages=810–5 |date=October 1982 |doi=10.1109/JSSC.1982.1051823 |url=}}</ref>

Line 49:

===Further development===

In the mid-1980s, faster CMOS variants, using similar HMOS process technology, such as Intel's CHMOS I, II, III, IV, etc. started to supplant n-channel HMOS for applications such as the [[Intel 80386]] and certain [[microcontroller]]s. A few years later, in the late 1980s, [[BiCMOS]] was introduced for high-performance microprocessors as well as for high speed [[analog circuit]]s. Today, most digital circuits, including the ubiquitous [[7400 series]], are manufactured using various CMOS processes with a range of different topologies employed. This means that, in order to enhance speed and save die area (transistors and wiring), high speed CMOS designs often employ other elements than just the [[:wikt:complementary|complementary]] ''[[CMOS|static]]'' [[logic gate|gate]]s and the [[transmission gate]]s of typical slow low-power CMOS circuits (the ''only'' CMOS type during the 1960s and 1970s). These methods use significant amounts of [[dynamic logic (digital logic)|dynamic]] circuitry in order to construct the larger building blocks on the chip, such as latches, decoders, multiplexers, and so on, and evolved from the various dynamic methodologies developed for pMOSNMOS and nMOSPMOS circuits during the 1970s.

==Compared to CMOS==

Compared to static CMOS, all variants of nMOSNMOS (and pMOSPMOS) are relatively power hungry in steady state. This is because they rely on load transistors working as [[resistor]]s, where the [[quiescent current]] determines the maximum possible load at the output as well as the speed of the gate (i.e. with other factors constant). This contrasts to the power consumption characteristics of ''static'' CMOS circuits, which is due only to the transient power draw when the output state is changed and the p- and n-transistors thereby briefly conduct at the same time. However, this is a simplified view, and a more complete picture has to also include the fact that even purely static CMOS circuits have significant leakage in modern tiny geometries, as well as the fact that modern CMOS chips often contain [[dynamic logic (digital logic)|dynamic]] and/or [[domino logic]] with a certain amount of ''pseudo nMOS'' circuitry.<ref>''Pseudo nMOS means that an enhancement-mode p-channel transistor with grounded gate is used in place of the depletion-mode n-channel transistor. See http://eia.udg.es/~forest/VLSI/lect.10.pdf''</ref>

== Evolution from preceding NMOS types ==

Line 60:

== Static power consumption ==

[[File:Nmos enhancement saturated nand.svg|right|thumb|An nMOSNMOS NAND gate with saturated enhancement-mode load device. The enhancement device can also be used with a more positive gate bias in a non-saturated configuration, which is more power efficient but requires a high gate voltage and a longer transistor. Neither is as power efficient or compact as a depletion load.]]

Depletion-load circuits consume less power than enhancement-load circuits at the same speed. In both cases the connection to ''1'' is always active, even when the connection to ''0'' is also active. This results in high static power consumption. The amount of waste depends on the strength, or physical size, of the pull-up. Both (enhancement-mode) saturated-load and depletion-mode pull-up transistors use greatest power when the output is stable at ''0'', so this loss is considerable. Because the strength of a depletion-mode transistor falls off less on the approach to ''1'', they may reach ''1'' faster despite starting slower, i.e. conducting less current at the beginning of the transition and at steady state.