Logic simulation: Difference between revisions

Revision as of 00:58, 3 January 2023

Revision as of 18:13, 4 January 2023

Line 4:

==Use in verification==

Logic simulation may be used as part of the [[Verification and validation|verification]] process in designing hardware.<ref name="ResearchGate">{{cite journal |last1=Bombieri |first1=Nicola |last2=Fummi |first2=Franco |last3=Pravadelli |first3=Graziano |title=Hardware Design and Simulation for Verification |journal=Lecture Notes in Computer Science |date=May 2006 |pages=1-291–29 |url=https://www.researchgate.net/publication/221224340_Hardware_Design_and_Simulation_for_Verification}}</ref>

Simulations have the advantage of providing a familiar look and feel to the user in that it is constructed from the same language and symbols used in design. By allowing the user to interact directly with the design, simulation is a natural way for the designer to get feedback on their design.

Line 19:

|author=Wang, Tsu-Hua and Tan, Chong Guan

|conference=1995 IEEE International Verilog HDL Conference

|pages=99-10499–104

|year=1995

|publisher=IEEE

Line 27:

|author=Jou, Jing-Yang and Liu, Chien-Nan Jimmy

|conference=Asia Pacific CHip Design Languages

|pages=48-55,48–55

|year=1999

|url=https://www.researchgate.net/profile/Chien-Nan-Liu/publication/266883269_Coverage_Analysis_Techniques_for_HDL_Design_Validation/links/54a566420cf256bf8bb4cf95/Coverage-Analysis-Techniques-for-HDL-Design-Validation.pdf}}</ref>