|
===x86 architecture===
{{Main|x86 memory segmentation}}
The memory segmentation used by earlyEarly [[x86]] processors, beginning with the [[Intel 8086]], doesprovide notcrude providememory anysegmentation and no [[memory protection]]. (Every Anybyte programof runningevery onsegment theseis processorsalways canavailable accessto any program.) The 16-bit segment withregisters noallow restrictions.for A65,536 segments; each segment isbegins onlyat identifieda byfixed itsoffset startingequal ___location;to there16 istimes nothe lengthsegment checking.number; Thethe segment starting address granularity is 16 bytes. andEach thesegment offsetgrants isread-write 16access bitsto 64 KiB (65,536 supportingbytes) segmentof sizesaddress upspace to(this 64limit KiB,is soset segmentsby canthe 16-bit PC (and oftenSP doregisters; the processor does no bounds checking). overlapOffset+address andexceeding 0xFFFFF wraps around to 0x00000. Each 64 KiB segment overlaps the next 4,095 segments; each physical address can be denoted by 40964,096 segmentsegment–offset pairs. This scheme can address only 1&ndashnbsp;offsetMiB pairs(1024 KiB) of physical memory (allowingand formemory-mapped addressi/o). offset(Optional [[expanded memory]] hardware can add wrapbank-aroundswitched memory under software control.) Intel retroactively named the sole operating mode of these x86 CPU models "[[real mode]]".
Segmentation in theThe [[Intel 80286]] and later providesprocessors protection: with theadd introduction of the 80286, Intel retroactively named the sole operating mode of the previous x86 CPU"286 models "[[realprotected mode]]", andwhich introducedprovides asegmentation newand "[[protectedper-segment mode]]" withmemory protection features. For backward compatibility, all x86 CPUs start up in "real mode", with the same fixed overlapping 64 KiB segments, no memory protection, fixedonly 641 KiBMiB segmentsphysical address space, and onlysome 20subtle differences ([[high memory area]], [[unreal mode]]). In order to use its full 24-bit (102416 KiBMiB) addressing.physical Anaddress space and advanced [[memory management unit|MMU]] features, an 80286 or later processor must be switched into another"protected mode" by software, inusually orderthe tooperating system or a [[DOS extender]]. If a program does not use itsthe fullsegment addressregisters, spaceor andonly advancedputs MMUvalues featuresin them that were supplied by the operating system, then it can run in real mode or protected mode, but most real-mode software computed new values for the segment registers, breaking this compatibility.
The [[Intel 80386i386]] and later processors alsoadd support"386 [[protected mode]]", which provides paging;. inIn those processors, the segment table, rather than pointing to a page table for the segment, contains the segment address in ''linear memory''. Addresses in linear memory are then mapped to physical addresses using a separate page table, if paging is enabled. Most operating systems did not use the segmentation capability, despite possible advantages (4 x 4GiB logical address space instead of only 4 GiB), opting to keep all segment registers equal to 0 ([[flat memory model]]).
The [[x86-64]] architecture does not usesupport segmentation in "[[long mode]]" (64-bit mode).<ref name=":1">{{Citecite book|url=https://www.amd.com/system/files/TechDocs/24594.pdf |title=AMD64 Technology AMD64 Architecture Programmer's Manual Volume 2: System Programming |publisher=Advanced Micro Devices|date=2018 |volume=2 |languagedate=en2018 |url=https://www.amd.com/system/files/TechDocs/24594.pdf}}</ref> In a [[X86-64|x86-64 architecture]] itarchitecture, segmentation is considered legacy, and most x86-64-based modern system software don't use memory segmentationit. Instead they handle programs and their data by utilizing [[Pagingpaging|memory- paging]] which also serves as a way of memory protection. Though most x86-64 implementations still support it for backward compatibility reasons.<ref name=":0" /> Four of the segment registers: CS, SS, DS, and ES are forced to 0, and the limit to 2<sup>64</sup>. The segment registers FS and GS can still have a nonzero base address. This allows operating systems to use these segments for special purposes.
== See also ==
|
