Signoff (electronic design automation): Difference between revisions

Revision as of 20:09, 28 January 2023

Revision as of 20:19, 28 January 2023

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== History ==

DurinDuring the late 1960s Duringengineers at semiconductor companies like Intel used [[rubylith]] for the semiconductor photomasks and layout design. Manually drawn [[Circuit diagram|circuit draft schematics]] of the semiconductor devices made by engineers were transeferred manually onto a [[Paper size|D-sized paper]] by skilled schematic designer to make a physical layout of the device.<ref name=":0">{{Cite journal |date=2001 |title=Recollections of Early Chip Development at Intel |url=https://deramp.com/downloads/mfe_archive/050-Component%20Specifications/Intel/Recollections%20of%20Early%20Chip%20Dev.pdf |journal=Intel technology journal |volume=5 |issue=2001 |issn=1535-864X}}</ref>{{r|:0|pp=6}}

The latter would be later hand-checked and ''signed off'' by the original engineer; all edits to the schematics would also be noted, checked, and, again, ''signed off''.{{r|:0|pp=6}}

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== Check types ==

Signoff checks have become more complex as [[VLSI]] designs approach [[22nm]] and below process nodes, because of the increased impact of previously ignored (or more crudely approximated) second-order effects. There are several categories of signoff checks.

* [[Layout Versus Schematic]] (LVS) – Also known as schematic verification, this is used to verify that the [[placement (electronic design automation)|placement]] and [[routing (electronic design automation)|routing]] of the [[standard cell]]s in the design has not altered the functionality of the constructed circuit.

* [[Design rule checking]] (DRC) – Also sometimes known as geometric verification, this involves verifying if the design can be reliably [[semiconductor fabrication|manufactured]] given current photolithography limitations. In advanced process nodes, [[Design for manufacturability (IC)|DFM]] rules are upgraded from optional (for better yield) to required.

*[[Layout Versus Schematic]] (LVS) – Also known as schematic verification, this is used to verify that the [[placement (electronic design automation)|placement]] and [[routing (electronic design automation)|routing]] of the [[standard cell]]s in the design has not altered the functionality of the constructed circuit.

* [[Formal verification]] – Here, the logical functionality of the post-[[Integrated circuit layout|layout]] netlist (including any layout-driven optimization) is verified against the pre-layout, post-[[logic synthesis|synthesis]] [[netlist]].

* [[Power network design (IC)|Voltage drop]] analysis – Also known as IR-drop analysis, this check verifies if the [[Power network design (IC)|power grid]] is strong enough to ensure that the [[IC power supply pin|voltage]] representing the binary '''high''' value never dips lower than a set margin (below which the circuit will not function correctly or reliably) due to the combined switching of millions of transistors.