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Line 44: * 32 KB [[CPU cache\|L1 data cache]] * 512 KB unified L2 cache, [[Set-associative#Associativity\|8-way set associative]] in the PPE variant. * Compatible with 64-bit PowerPC ISA v.2.02 ([[POWER4]] and [[PowerPC 970]])<ref name="the-ppe">{{cite book \|url= https://link.springer.com/chapter/10.1007/978-1-4419-0308-2_2 \|title=Practical Computing on the Cell Broadband Engine \|first=Sandeep \|last=Koranne \|chapter=The Power Processing Element (PPE) \|chapter-url=https://link.springer.com/chapter/10.1007/978-1-4419-0308-2_2 ~~\|chapter=Chapter 2 - The Power Processing Element (PPE)~~ \|isbn=978-1-4419-0307-5 \|publisher=[[Springer Science+Business Media]] \|date=July 15, 2009\|pages=17–34 \|doi=10.1007/978-1-4419-0308-2_2 }}</ref>{{rp\|page=17}} * [[AltiVec]] [[SIMD]] functionality

Power Processing Element: Difference between revisions