Predication (computer architecture): Difference between revisions

Revision as of 09:09, 12 March 2023

Revision as of 09:11, 12 March 2023

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[[Vector processors]], some [[SIMD]] ISAs (such as [[AVX2]] and [[AVX-512]]) and [[GPU]]s in general make heavy use of predication, applying one bit of a conditional ''mask Vectorvector'' to the corresponding elements in the Vectorvector registers being processed, whereas scalar predication in scalar instruction sets only need the one predicate bit. Where Predicatepredicate Masksmasks become particularly powerful in [[Vectorvector processing]] is if an ''array'' of [[Condition_code_registercondition_code_register|Conditioncondition Codescodes]], one per Vectorvector element, may feed back into Predicatepredicate Masksmasks that are then applied to subsequent Vectorvector instructions.

==Overview==