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{{Distinguish|branch prediction}}
In [[computer architecture]], '''predication''' is a feature that provides an alternative to [[Conditional (computer programming)|conditional]] transfer of [[control flow|control]], as implemented by conditional [[branch (computer science)|branch]] machine [[instruction (computer science)|instructions]]. Predication works by having conditional (''predicated'') non-branch instructions associated with a ''predicate'', a [[Boolean data type|Boolean value]] used by the instruction to control whether the instruction is allowed to modify the architectural state or not. If the predicate specified in the instruction is true, the instruction modifies the architectural state; otherwise, the architectural state is unchanged. For example, a predicated move instruction (a conditional move) will only modify the destination if the predicate is true. Thus, instead of using a conditional branch to select an instruction or a sequence of instructions to [[Execution (computing)|execute]] based on the predicate that controls whether the branch occurs, the instructions to be executed are associated with that predicate, so that they will be executed, or not executed, based on whether that predicate is true or false.<ref name="rvinyard">{{cite web |author=Rick Vinyard |date=2000-04-26 |title=Predication |url=https://www.cs.nmsu.edu/~rvinyard/itanium/predication.htm |archive-url=https://web.archive.org/web/20150420152310/https://www.cs.nmsu.edu/~rvinyard/itanium/predication.htm |archive-date=20 Apr 2015 |accessdate=2014-04-22 |website=cs.nmsu.edu}}</ref>
[[Vector processors]], some [[SIMD]] ISAs (such as [[AVX2]] and [[AVX-512]]) and [[GPU]]s in general make heavy use of predication, applying one bit of a conditional ''mask vector'' to the corresponding elements in the vector registers being processed, whereas scalar predication in scalar instruction sets only need the one predicate bit. Where predicate masks become particularly powerful in [[vector processing]] is if an ''array'' of [[condition_code_register|condition codes]], one per vector element, may feed back into predicate masks that are then applied to subsequent vector instructions.
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