Atmel AVR instruction set: Difference between revisions

Revision as of 00:00, 12 April 2023

Revision as of 15:21, 15 April 2023

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#* It is not necessary to explicitly disable interrupts before adjusting the stack pointer registers (SPL and SPH); any write to SPL automatically disables interrupts for 4 clock cycles to give time for SPH to be updated.<!--Technically, until the next I/O write (presumably SPH) or 4 cycles, whichever comes first-->

#* Other multi-byte registers are provided with shadow registers to enable [[Atomic operation|atomic]] read and write. When the lowest-order byte is read, the higher-order bytes are copied to the shadow registers, so reading them later produces a [[snapshot (computer storage)|snapshot]] of the register at the time of the first read. Writes to low-order bytes are buffered until the highest-order byte is written, upon which the entire multi-byte register is updated atomically.

# Later XMEGA cores (specifically, the B, C, and AU models such as the ATxmega16A4U , but ''not'' the earlier A, D and E models such as the ATxmega16D4) add four atomic [[read-modify-write]] instructions: exchange (<code>XCH</code>), load-and-set, load-and-clear, and load-and-toggle.<!--This is from the avr-mcus.def file in the GCC sources, and doesn't match the data sheets, but Atmel redesigned those in 2016 and introduced a lot of errors; many have changelogs mentioning "deleted DES instruction" suggesting they cut & pasted the instruction list and didn't delete unsupported instructions properly. --> These help coordinate with [[direct memory access]] peripherals, notably a [[USB]] controller.

Less capable than the "classic" CPU cores are two subsets: the "AVR1" core, and the "AVR tiny". Confusingly, "ATtiny" branded processors have a variety of cores, including AVR1 (ATtiny11, ATtiny28), classic (ATtiny22, ATtiny26), classic+ (ATtiny24) and AVRtiny (ATtiny20, ATtiny40).

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! scope=row | Enhanced Core with up to 8K ("AVR4")

| {{ublist|ATmega8|ATmega83|ATmega85|ATmega8515}}

| new instructions:{{ublist|item_style=font-family:monospace;|MUL|MULS|MULSU|FMUL|FMULS|FMULSU<ref> Atmel. [http://www.atmel.com/Images/doc1631.pdf Application Note "AVR201: Using the AVR Hardware Multiplier"]. 2002. quote: "The megaAVR is a series of new devices in the AVR RISC Microcontroller family that includes, among other new enhancements, a hardware multiplier."</ref>}}

| {{CNone|(nothing new)}}

| new instructions:{{ublist|{{mono|MOVW}}|{{mono|LPM}} (3 modes)|{{mono|SPM}}}}

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*[http://starlo.org/blake/boardmicro/ AVR Instruction Set Simulator (ATmega32u4 for GCC Intel Hex Files)]

*[https://github.com/avr-llvm/architecture/blob/master/Instructions/inheritance.md AVR Instruction Set Inheritance] (LLVM note), based on this page and GCC & Binutils code

{{DEFAULTSORT:Atmel Avr Instruction Set}}

[[Category:Atmel microcontrollers]]