Transaction-level modeling: Difference between revisions

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{{Short description|Approach for digital systems design}}

'''Transaction-level modeling''' ('''TLM''') is an approach to modelling complex digital systems by using [[electronic design automation]] software.<ref name="TVLSIHB-2007">{{Cite book |url=https://www.worldcat.org/oclc/70699056 |title=The VLSI handbook |date=2007 |publisher=CRC/Taylor & Francis |others=Wai-Kai Chen |isbn=978-0-8493-4199-1 |edition=2 |___location=Boca Raton, FL |oclc=70699056}}</ref>{{Rp|page=1955}} TLM is used primarily in the design and verification of complex [[System-on-a-chip|systems-on-chip]] (SoCs) and other electronic systems where traditional [[Register-transfer level|register-transfer level]] (RTL) modeling would be too slow or resource-intensive for system-level analysis. TLM language (TLML) is a [[hardware description language]], usually, written in C++ and based on [[SystemC]] library.<ref name="TVLSIHB-2007" /> TLMLs are used for modelling where details of communication among modules are separated from the details of the implementation of functional units or of the communication architecture. It's used for modelling of systems that involve complex data communication mechanisms.{{r|TVLSIHB-2007|pp=1955}} The modeling approach focuses on the ''transactions'' or ''transfers'' of data between functional blocks rather than the detailed implementation of those blocks or their interconnections.<ref name="IEEE_TLM_Standard">{{cite journal |title=IEEE Standard for Standard SystemC Language Reference Manual |journal=IEEE Std 1666-2011 |year=2012 |doi=10.1109/IEEESTD.2012.6134619}}</ref> This abstraction enables faster simulation speeds, often orders of magnitude faster than RTL, while maintaining sufficient accuracy for system-level design decisions, [[software development]], and architectural exploration.<ref name="Ghenassia_TLM">{{cite book |title=Transaction-Level Modeling with SystemC |editor=Ghenassia, Frank |publisher=Springer |year=2005 |isbn=978-0-387-26233-4}}</ref>

Components such as buses or [[FIFO (computing and electronics)|FIFOs]] are modeled as channels, and are presented to modules using [[SystemC]] interface classes. Transaction requests take place by calling interface functions of these channel models, which encapsulate low-level details of the information exchange. At the transaction level, the emphasis is more on the functionality of the data transfers – what data are transferred to and from what locations – and less on their actual implementation, that is, on the actual protocol used for data transfer. This approach makes it easier for the system-level designer to experiment, for example, with different bus architectures (all supporting a common abstract interface) without having to recode models that interact with any of the buses, provided these models interact with the bus through the common interface.<ref>T. Grötker, S. Liao, G. Martin, S. Swan, System Design with SystemC. Springer, 2002, Chapter 8., pp. 131. {{ISBN|1-4020-7072-1}} (quoted with permission)</ref>

TLM is typically implemented using [[SystemC]], a [[C++]]-based modeling language and library developed specifically for system-level design.<ref name="SystemC_Standard">{{cite web |url=https://www.accellera.org/downloads/standards/systemc |title=SystemC Standards |publisher=Accellera Systems Initiative |access-date=2024-01-15}}</ref> The [[Open SystemC Initiative]] (OSCI), now part of [[Accellera]], has developed standardized TLM libraries that provide common interfaces and methodologies for transaction-level communication. However, the application of transaction-level modeling is not specific to the SystemC language and can be used with other languages. The concept of TLM first appears in systemthe system-level language and modeling ___domain.<ref>L. Cai, D. Gajski, Transaction Level Modeling: An Overview, in proceedings of the Int. Conference on HW/SW Codesign and System Synthesis (CODES-ISSS), Oct. 2003, pp. 19–24</ref>

TransactionThe methodology has become essential in modern [[electronic design automation]] (EDA) flows, particularly for creating [[virtual platform]]s that enable early [[software development]] and system validation before hardware implementation is complete.<ref name="Virtual_Platforms">{{cite conference |title=Virtual Platforms in System-levelLevel Design |author=Schirner, Gunar |conference=Design Automation Conference |year=2013 |pages=804-809 |doi=10.1145/2463209.2488885}}</ref> TLM models serve as executable specifications that bridge the gap between high-level system requirements and detailed hardware implementations. TLMs are used for [[high-level synthesis]] of [[register-transfer level]] (RTL) models for a lower-level modelling and implementation of system components. RTL is usually represented by a [[hardware description language]] source code (e.g. [[VHDL]], [[SystemC]], [[Verilog]]).{{r|TVLSIHB-2007|pp=1955-1957}}

==Background and History==

In 2000, Thorsten Grötker, R&D Manager at [[Synopsys]] was preparing a presentation on the communication mechanism in what was to become the [[SystemC]] 2.0 standard, and referred to it as "transaction-based modeling". Gilles Baillieu, then a corporate application engineer at Synopsys, insisted that the new term had to contain "level", as in "[[register-transfer level]]" or "behavioral level". The fact that TLM does not denote a single level of abstraction but rather a modeling technique didn't make him change his mind. It had to be "level" in order to make it stick. So it became "TLM".{{Citation needed|date=March 2008}}

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Since those early days SystemC has been adopted as the language of choice for high level synthesis, connecting the design modeling and virtual prototype application domains with the functional verification and automated path gate level implementation. This offers project teams the ability to produce one model for multiple purposes. At the 2010 DVCon event, OSCI produced a specification of the first synthesizable subset of SystemC for industry standardization.

==Key Concepts==

==See also==