Cell microprocessor implementations: Difference between revisions

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====SPE power and performance====
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As tested by IBM under a heavy transformation and lighting workload [average IPC of 1.4], the performance profile of this implementation for a single SPU processor is qualified as follows:
 
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|+ Relationship of speed to temperature
! Voltage (V) !! Frequency (GHz) !! Power (W) !! Die tempTemp. (°C)
|-
| 0.9 V || 2.0 GHz || {{0}}1 W || 25 °C
|-
| 0.9 V || 3.0 GHz || {{0}}2 W || 27 °C
|-
| 1.0 V || 3.8 GHz || {{0}}3 W || 31 °C
|-
| 1.1 V || 4.0 GHz || {{0}}4 W || 38 °C
|-
| 1.2 V || 4.4 GHz || {{0}}7 W || 47 °C
|-
| 1.3 V || 5.0 GHz || 11 W || 63 °C
|}
As tested by IBM under a heavy transformation and lighting workload [average IPC of 1.4], the performance profile of this implementation for a single SPU processor is qualified as follows:
 
The entry for 2.0 GHz operation at 0.9 V represents a low power configuration. Other entries show the peak stable operating frequency achieved with each voltage increment. As a general rule in CMOS circuits, power dissipation rises in a rough relationship to V{{sup|2}}F, the square of the voltage times the operating frequency.