Segger Microcontroller Systems: Difference between revisions

Revision as of 15:59, 9 August 2023

Revision as of 21:37, 10 August 2023

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|+ <big>J-Trace & J-Link Models</big><ref>[http://www.segger.com/jlink-model-overview.html J-Link Model Overview; segger.com]</ref>

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! Model !! Host<br/>[[USB#Version history|USB]]<br />&nbsp; !! Host<br/>[[Ethernet physical layer|Ethernet]]<br />&nbsp; !! Host<br/>[[Wi-Fi]]<br />&nbsp; !! Debug<br />[[Pin header|connector]]<br />([[Pitch (electronics)|Pitch]]) !! Trace<br/>[[Pin header|connector]]<br />&nbsp; !! Target<br/>[[volt]]age<br />&nbsp; !! Target max<br />interface<br />speed !! Target max<br />download<br />speed !! Target<br />[[Virtual COM port|VCOM]]<br />[[Universal asynchronous receiver-transmitter|UART]] !! Software<br />features<br />&nbsp; !! Image<br />&nbsp;</br />&nbsp;

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| style="text-align:left" | J-Trace PRO Cortex-A/R/M || 3.0 SS || {{yes|1 Gbit/s}} || None || 20-pin (0.1") || {{yes|19-pin 0.05"}} || 1.2V to 5V || 50&nbsp;[[MHz]] || 3 MByte/s || 2 pins || All || [[File:J-Trace Cortex-ARM 1349x1466 230627.png|95px]]