Depletion-load NMOS logic: Difference between revisions

Revision as of 15:05, 14 September 2023

Revision as of 15:09, 14 September 2023

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Early MOS logic had one transistor type, which is [[enhancement mode]] so that it can act as a logic switch. Since suitable resistors were hard to make, the logic gates used saturated loads; that is, to make the one type of transistor act as a load resistor, the transistor had to be turned always on by tying its gate to the power supply (the more negative rail for [[PMOS logic]], or the more positive rail for [[NMOS logic]]). Since the current in a device connected that way goes as the square of the voltage across the load, it provides poor pullup speed relative to its power consumption when pulled down. A resistor (with the current simply proportional to the voltage) would be better, and a current source (with the current fixed, independent of voltage) better yet. A [[depletion-mode]] device with gate tied to the opposite supply rail is a much better load than an enhancement-mode device, acting somewhere between a resistor and a current source.

The first depletion-load NMOS circuits were pioneered and made by the [[Dynamic random-access memory|DRAM]] manufacturer [[Mostek]], which made depletion-mode transistors available for the design of the original [[Zilog Z80]] in 1975–76.<ref>''Zilog relied on [[Mostek]] and [[Synertek]] to produce the Z80 and other chips before their own production facilities were ready.''</ref> Mostek had the [[ion implantation]] equipment needed to create a [[doping (semiconductor)|doping profile]] more precise than possible with [[diffusion]] methods, so that the [[threshold voltage]] of the load transistors could be adjusted reliably. At Intel, depletion load was introduced in 1974 by Federico Faggin, an ex-Fairchild engineer and later the founder of [[Zilog]]. Depletion-load was first employed for a redesign of one of Intel's most important products at the time, a +5V-only 1Kbit NMOS [[Static random-access memory|SRAM]] called the ''2102'' (using more than 6000 transistors<ref>''Each bit demands six transistors in a typical [[static random-access memory|static RAM]].''</ref>). The result of this redesign was the significantly faster ''2102A'', where the highest performing versions of the chip had access times of less than 100ns, taking MOS memories close to the speed of bipolar RAMs for the first time.<ref>''See for instance: http://www.intel4004.com/sgate.htm or http://archive.computerhistory.org/resources/text/Oral_History/Faggin_Federico/Faggin_Federico_1_2_3.oral_history.2004.102658025.pdf'' {{Webarchive|url=https://web.archive.org/web/20170110232713/http://archive.computerhistory.org/resources/text/Oral_History/Faggin_Federico/Faggin_Federico_1_2_3.oral_history.2004.102658025.pdf |date=2017-01-10 }}</ref>

Depletion-load NMOS processes were also used by several other manufacturers to produce many incarnations of popular 8-bit, 16-bit, and 32-bit CPUs. Similarly to early PMOS and NMOS CPU designs using [[Channel (transistor)|enhancement mode]] MOSFETs as loads, depletion-load nMOS designs typically employed various types of [[dynamic logic (digital electronics)|dynamic logic]] (rather than just static gates) or [[Pass transistor logic|pass transistor]]s used as dynamic [[Flip-flop (electronics)|clocked latch]]es. These techniques can enhance the area-economy considerably although the effect on the speed is complex. Processors built with depletion-load NMOS circuitry include the [[Motorola 6800|6800]] (in later versions<ref name = "M6800 redesign">{{Cite journal| title = Motorola Redesigns 6800 | journal = Microcomputer Digest | volume = 3 | issue = 2 | page =4 | publisher = Microcomputer Associates | ___location = Santa Clara, CA | date = August 1976 | url = http://www.bitsavers.org/pdf/microcomputerAssociates/Microcomputer_Digest_v03n02_Aug76.pdf}} "Motorola is redesigning the M6800 microprocessor family by adding depletion loads to increase speed and reduce the 6800 CPU size to 160 mils."</ref>), the [[MOS Technology 6502|6502]], [[Signetics 2650]], [[Intel 8085|8085]], [[Motorola 6809|6809]], [[Intel 8086|8086]], [[Zilog Z8000|Z8000]], [[NS32000|NS32016]], and many others (whether or not the HMOS processors below are included, as special cases).

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The original HMOS process, later referred to as HMOS I, had a channel length of 3 microns, which was reduced to 2 for the HMOS II, and 1.5 for HMOS III. By the time HMOS III was introduced in 1982, Intel had begun a switch to their [[CHMOS]] process, a [[CMOS]] process using design elements of the HMOS lines. One final version of the system was released, HMOS-IV. A significant advantage to the HMOS line was that each generation was deliberately designed to allow existing layouts to die-shrink with no major changes. Various techniques were introduced to ensure the systems worked as the layout changed.<ref>{{cite conference |conference=ISSCC 82 |date=1982 |title=HMOS III Technology}}</ref><ref>{{cite journal |first1=G.E. |last1=Atwood |first2=H. |last2=Dun |first3=J. |last3=Langston |first4=E. |last4=Hazani |first5=E.Y. |last5=So |first6=S. |last6=Sachdev |first7=K. |last7=Fuchs |title=HMOS III technology |journal=IEEE Journal of Solid-State Circuits |volume=17 |issue=5 |pages=810–5 |date=October 1982 |doi=10.1109/JSSC.1982.1051823 |bibcode=1982IJSSC..17..810A |s2cid=1215664 |url=}}</ref>

HMOS, HMOS II, HMOS III, and HMOS IV were together used for many different kinds of processors; the [[Intel 8085|8085]], [[Intel MCS-48|8048]], [[Intel 8051|8051]], [[Intel 8086|8086]], [[Intel 18680186|80186]], [[Intel 28680286|80286]], and many others, but also for several generations of the same basic design, see [[datasheet]]s.

===Further development===

In the mid-1980s, faster CMOS variants, using similar HMOS process technology, such as Intel's CHMOS I, II, III, IV, etc. started to supplant n-channel HMOS for applications such as the [[i386|Intel 80386]] and certain [[microcontroller]]s. A few years later, in the late 1980s, [[BiCMOS]] was introduced for high-performance microprocessors as well as for high speed [[analogue electronics|analog circuitcircuits]]s. Today, most digital circuits, including the ubiquitous [[7400 series]], are manufactured using various CMOS processes with a range of different topologies employed. This means that, in order to enhance speed and save die area (transistors and wiring), high speed CMOS designs often employ other elements than just the [[:wikt:complementary|complementary]] ''[[CMOS|static]]'' [[logic gate|gate]]s and the [[transmission gate]]s of typical slow low-power CMOS circuits (the ''only'' CMOS type during the 1960s and 1970s). These methods use significant amounts of [[dynamic logic (digital logicelectronics)|dynamic]] circuitry in order to construct the larger building blocks on the chip, such as latches, decoders, multiplexers, and so on, and evolved from the various dynamic methodologies developed for NMOS and PMOS circuits during the 1970s.

==Compared to CMOS==