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Note that both the Maevsky and Tsirlin circuits are based actually on so-called David cell.<ref>[https://ieeexplore.ieee.org/document/4244956 M. Courvoisier and P. Azema, "Asynchronous sequential machines with request/acknowledge operating mode," IEE Electronics Letters, Vol. 10, no. 1, pp.8-10, 1974.]</ref> Its fast transistor-level implementation is used in the semistatic C-element proposed.<ref>S. M. Fairbanks, [http://worldwide.espacenet.com/publicationDetails/originalDocument?CC=US&NR=6281707B1&KC=B1&FT=D&ND=3&date=20010828&DB=EPODOC&locale=en_EP "Two-stage Muller C-element"], United States Patent US6281707, Aug. 28, 2001.</ref> Yet another semistatic circuit using pass transistors (actually MUX 2:1) has been proposed.<ref>A. Morgenshtein, M. Moreinis, R. Ginosar, [http://webee.technion.ac.il/~ran/papers/Async-GDI-circuits-Nov02.pdf "Asynchronous gate-diffusion-input (GDI) circuits"], IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 8, pp. 847–856, 2004.</ref>. Yet another version of the C-element built on two [[RS latch#Simple set-reset latches|SR-latches]] has been synthesized by Murphy<ref>J. P. Murphy, [http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6317230 "Design of latch-based C-element"], Electronics Letters, vol. 48, no. 19, 2012, pp. 1190–1191.</ref> using Petrify tool. However, this circuit includes inverter connected to one of the inputs. This inverter should have small delay. However, there are realizations of RS latches that already have one inverted input, for example.<ref>V. A. Maksimov and Ya. Ya. Petrichkovich [https://yandex.ru/patents/doc/SU1164867A1_19850630 "RS flip-flop,"] USSR author's certificate SU1164867, Jun. 30, 1985.</ref> Some speed-independent approaches<ref>P. Beerel and T. H.-Y. Meng. [http://dl.acm.org/citation.cfm?id=304171 "Automatic gate-level synthesis of speed-independent circuits"], IEEE/ACM Int. Conference on Computer-Aided Design (ICCAD) 1992, pp. 581–587.</ref><ref>A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev, [http://dl.acm.org/citation.cfm?id=196275 "Basic gate implementation of speed-independent circuits"], ACM Design Automation Conference (DAC) 1994, pp. 56–62.</ref> assume that zero-delay input inverters are available on all gates, which is a violation of true speed-independence but is fairly safe in practice. Other examples of using this assumption also exist.<ref>A. V. Yakovlev, A. M. Koelmans, A. Semenov, D. J. Kinniment, [http://www.sciencedirect.com/science/article/pii/S0167926096000107 "Modelling, analysis and synthesis of asynchronous control circuits using Petri nets"], Integration, the VLSI Journal, vol. 21, no. 3, pp. 143—170, 1996.</ref>
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Other technologies suitable for realizing asynchronous primitives including C-element, are: carbon nanotubes,{{Citation needed|date=December 2019|reason=removed citation to predatory publisher content}} single-electron tunneling devices,<ref>S. Safiruddin, S. D. Cotofana, [https://www.researchgate.net/profile/Sorin_Cotofana/publication/224326348_Building_Blocks_for_Delay-Insensitive_Circuits_using_Single_Electron_Tunneling_Devices/links/0c9605230deb723cac000000.pdf "Building blocks for delay-insensitive circuits using single electron tunneling devices"], IEEE Conference on Nanotechnology 2007, pp. 704–708.</ref> quantum dots,<ref>V. I. Varshavsky, [http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=494973 "Logic design and quantum challenge"], Int. Workshop on Physics and Computer Modeling of Devices Based on Low-Dimensional Structures 1995, pp. 134–146.</ref> and molecular nanotechnology.<ref>A. J. Martin, P. Prakash, [http://www.async.caltech.edu/Pubs/PDF/2008_nano.pdf "Asynchronous nano-electronics: Preliminary investigation"] {{Webarchive|url=https://web.archive.org/web/20160304122447/http://www.async.caltech.edu/Pubs/PDF/2008_nano.pdf |date=2016-03-04 }}, IEEE Int. Symposium on Asynchronous Circuits and Systems (ASYNC) 2008, pp. 58–68.</ref>▼
===Generalization for multiple-valued logic===
The definition of C-element can be generalized for multiple-valued logic,<ref name="Kim69" /><ref>[https://www.proquest.com/docview/303676273?pq-origsite=gscholar&fromopenview=true J. M. Johnson, Theory and Application of Self-Timed Integrated Systems Using Ternary Logic Elements. PhD thesis. University of California, Santa Barbara. 1989.]</ref> or even for continuous signals:
:<math>\text { if } x_1=x_2=...=x_m, \text { then } y_n=\text{any}(x_1,x_2,...,x_m), \text { else } y_n=y_{n-1}.</math>
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\end{cases}</math>
does not lead to the ternary C-element specified by the truth table, if the sum <math>x_1 + x_2 + x_3</math> is not split into pairs. However, even without such a splitting two ternary majority functions are suitable for building a ternary inclusive OR gate.
▲Other technologies suitable for realizing asynchronous primitives including C-element, are: carbon nanotubes,{{Citation needed|date=December 2019|reason=removed citation to predatory publisher content}} single-electron tunneling devices,<ref>S. Safiruddin, S. D. Cotofana, [https://www.researchgate.net/profile/Sorin_Cotofana/publication/224326348_Building_Blocks_for_Delay-Insensitive_Circuits_using_Single_Electron_Tunneling_Devices/links/0c9605230deb723cac000000.pdf "Building blocks for delay-insensitive circuits using single electron tunneling devices"], IEEE Conference on Nanotechnology 2007, pp. 704–708.</ref> quantum dots,<ref>V. I. Varshavsky, [http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=494973 "Logic design and quantum challenge"], Int. Workshop on Physics and Computer Modeling of Devices Based on Low-Dimensional Structures 1995, pp. 134–146.</ref> and molecular nanotechnology.<ref>A. J. Martin, P. Prakash, [http://www.async.caltech.edu/Pubs/PDF/2008_nano.pdf "Asynchronous nano-electronics: Preliminary investigation"] {{Webarchive|url=https://web.archive.org/web/20160304122447/http://www.async.caltech.edu/Pubs/PDF/2008_nano.pdf |date=2016-03-04 }}, IEEE Int. Symposium on Asynchronous Circuits and Systems (ASYNC) 2008, pp. 58–68.</ref>
==References==
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