[[x86-64]] processors without this feature use a four-level page table structure when operating in 64-bit mode.<ref name="x86-software-developers-manual" />{{Rp|2806page=4{{hyp}}22}} A similar situation arose when the 32 bit [[IA-32]] processors used two levels, allowing up to four [[gigabyte|GB]] of memory (both virtual and physical). To support more than 4 GB of [[RAM]], an additional mode of address translation called [[Physical Address Extension]] (PAE) was defined, involving a third level.<ref>{{Cite web|url=https://docs.microsoft.com/en-us/previous-versions/windows/hardware/design/dn613969(v=vs.85)|title=Operating Systems and PAE Support - Windows 10 hardware dev|last=Hudek|first=Ted|website=docs.microsoft.com|date=June 2017 |language=en-us|access-date=2018-04-26}}</ref> This was enabled by setting a bit in [[Control register#CR4|the CR4 register]].<ref name="x86-software-developers-manual" />{{Rp|2799page=4{{hyp}}14}} Likewise, the new extension is enabled by setting bit 12 of the CR4 register (known as LA57).<ref name="intel-white-paper" />{{Rp|16}} This is only used when the processor is operating in 64 bit mode, and only may be modified when it is not.<ref name="intel-white-paper" />{{Rp|16}} If the bit is not set, the processor operates with four paging levels.
As adding another page table multiplies the address space by 512, the virtual limit has increased from 256 TB to 128 PB. An extra nine bits of the virtual address index the new table, so while formerly bits 0 through 47 were in use, now bits 0 through 56 are in use.
As with four level paging, the high-order bits of a virtual address that do not participate in address translation must be the same as the most significant implemented bit. With five-level paging enabled, this means that bits 57 through 63 must be copies of bit 56.<ref name="intel-white-paper" />{{Rp|17}} Intel has renamed the existing paging system as "4-level paging", which used to be known as [[IA-32e]] paging.<ref name="x86-software-developers-manual" />{{Rp|2788page=4{{hyp}}2}}
Extending page table entry to 128 bits allows full 64-bit address space in 4-level paging scheme, and makes possible arbitrary allocation unit sizes in 5-level scheme.<Ref name=VA64/>
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== Drawbacks ==
Adding another level of indirection makes [[page table]] "walks" longer.<ref>{{Cite book|title=MICRO-50 : the 50th Annual IEEE/ACM International Symposium on Microarchitecture : proceedings : October 14-18, 2017, Cambridge, MA|others=Institute of Electrical and Electronics Engineers., IEEE Computer Society., ACM Special Interest Group on Microprogramming|isbn=9781450349529|___location=New York, New York|oclc=1032337814|date = 14 October 2017}}</ref> A page table walk occurs when either the processor's [[memory management unit]] or the memory management code in the operating system navigates the tree of page tables to find the [[page table entry]] corresponding to a virtual address.<ref>{{Cite web|url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0301h/I1026235.html|title=ARM Information Center|website=infocenter.arm.com|access-date=2018-04-26}}</ref><ref name="x86-software-developers-manual">{{Cite book|url=https://softwarewww.intel.com/sitescontent/defaultwww/filesus/manageden/39developer/c5articles/325462technical/intel-sdm-vol-1-2abcd-3abcd.pdfhtml|title=Intel® 64 and IA-32 Architectures Software Developer's Manual|volume=3A|publisher=[[Intel Corporation]]|year=2018}}</ref>{{Rp|2806page=4{{hyp}}22}} This means that, in the worst case, the processor or the memory manager has to access physical memory six times for a single virtual memory access, rather than five for the previous iteration of x86-64 processors. This results in slightly reduced memory access speed.<ref name="cse-451-paging-tlbs-slides" /> In practice this cost is greatly mitigated by caches such as the [[translation lookaside buffer]] (TLB).<ref name="cse-451-paging-tlbs-slides">{{Cite web|url=https://courses.cs.washington.edu/courses/cse451/08au/lectures/10-paging_TLBs.pdf|title=CSE 451: Operating Systems: Paging & TLBs|last=Levy|first=Hank|author-link=Hank Levy (computer scientist)|date=Autumn 2008|website=[[University of Washington]]|access-date=26 April 2018}}</ref> Further extensions may reduce page walks by using 4096 128-bit page table entries, and allow a larger 64 KB [[Page (computer memory)|page size]] and backward compatibility with 4 KB page operations.<Ref name=VA64>{{cite patent | country = US | number = 9858198 | status = patent | title = 64KB page system that supports 4KB page operation | pridate = 2015-06-26 | fdate = 2015-06-26 | pubdate = 2016-12-29 | gdate = 2018-01-02 | invent1 = Larry Seiler | assign1 = Intel Corp.}} </ref>
