Intel 5-level paging: Difference between revisions

Revision as of 21:25, 27 January 2024

Revision as of 21:06, 24 February 2024

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== Technology ==

In the 4-level paging scheme (previously known as [[IA-32e]] paging), the 64-bit virtual memory address is divided into five parts. The lowest 12 bits contain the offset within the 4 KiB memory page, and the following 36 bits are evenly divided between the four 9 bit descriptors, each linking to a 64-bit page table entry in a 512-entry page table for each of the four paging levels. This makes it possible to use bit 0 through 47 in the virtual address, for a total of 256&nbsp;TB. <ref name="x86-software-developers-manual" />{{Rp|page=4{{hyp}}2}}

[[x86-64]] processors without this feature use a four-level page table structure when operating in 64-bit mode.<ref name="x86-software-developers-manual" />{{Rp|page=4{{hyp}}22}} A similar situation arose when the 32 bit [[IA-32]] processors used two levels, allowing up to four [[gigabyte|GB]] of memory (both virtual and physical). To support more than 4&nbsp;GB of [[RAM]], an additional mode of address translation called [[Physical Address Extension]] (PAE) was defined, involving a third level.<ref>{{Cite web|url=https://learn.microsoft.com/en-us/previous-versions/windows/hardware/design/dn613969(v=vs.85)|title=Operating Systems and PAE Support - Windows 10 hardware dev|last=Hudek|first=Ted|website=[[Microsoft Learn]]|date=June 2017 |language=en-us|access-date=2024-01-27}}</ref> This was enabled by setting a bit in [[Control register#CR4|the CR4 register]].<ref name="x86-software-developers-manual" />{{Rp|page=4{{hyp}}14}} Likewise, the new extension is enabled by setting bit 12 of the CR4 register (known as LA57).<ref name="intel-white-paper" />{{Rp|16}} This is only used when the processor is operating in 64 bit mode, and only may be modified when it is not.<ref name="intel-white-paper" />{{Rp|16}} If the bit is not set, the processor operates with four paging levels.

As5-level addingpaging adds another 9 bit page table multiplies the address space by 512descriptor, themaking virtualit limitpossible hasto increaseduse from 256bits&nbsp;TB0 to 128through&nbsp;PB56. AnThis extra nine bits ofmultiplies the virtual address indexspace theby new512 table,and soincreases whilethe formerlylimit bits&nbsp;0to through128&nbsp;47 were in use, now bits&nbsp;0 through&nbsp;56 are in usePB.

As with four level paging, the high-order bits of a virtual address that do not participate in address translation must be the same as the most significant implemented bit. With five5-level paging enabled, this means that bits&nbsp;57 through&nbsp;63 must be copies of bit&nbsp;56.<ref name="intel-white-paper" />{{Rp|17}} IntelThis has renamedis the existingsame pagingas systemwith as "4-level paging", whichwhere usedthe tohigh-order bits of a virtual address that do not participate in address translation must be knownthe same as [[IA-32e]]the paging.<refmost name="x86-software-developers-manual"significant />{{Rp|page=4{{hyp}}2}}implemented bit.

The 5-level paging is enabled by setting bit 12 of the CR4 register (known as LA57).<ref name="intel-white-paper" />{{Rp|16}} This is only used when the processor is operating in 64 bit mode, and only may be modified when it is not.<ref name="intel-white-paper" />{{Rp|16}} If the bit is not set, or the 5-level paging feature is not supported, the processor uses the 4-level page table structure when operating in 64-bit mode.<ref name="x86-software-developers-manual" />{{Rp|page=4{{hyp}}22}} This is similar to [[Physical Address Extension]] (PAE), where the third level of paging tables was enabled by setting a bit in [[Control register#CR4|the CR4 register]].<ref>{{Cite web|url=https://learn.microsoft.com/en-us/previous-versions/windows/hardware/design/dn613969(v=vs.85)|title=Operating Systems and PAE Support - Windows 10 hardware dev|last=Hudek|first=Ted|website=[[Microsoft Learn]]|date=June 2017 |language=en-us|access-date=2024-01-27}}</ref><ref name="x86-software-developers-manual" />{{Rp|page=4{{hyp}}14}}

Future processors may allow full 64-bit virtual address space by extending the size of page table descriptors to 12 bits (4096 page table entries) and memory offset to 16 bits (64 KiB page size) in the 4-level paging scheme or 21 bits (2 MiB page size) in the 5-level scheme.<Ref name=VA64/> Extending page table entry size would allow arbitrary page sizes, as additional hardware flags would change the size and operation of descriptors on lower paging levels.<Ref name=VA64/>

Extending page table entry to 128 bits allows full 64-bit address space in 4-level paging scheme, and makes possible arbitrary allocation unit sizes in 5-level scheme.<Ref name=VA64/>

== Implementation ==