Field-programmable gate array: Difference between revisions

Revision as of 17:21, 10 February 2024

Revision as of 17:25, 10 February 2024

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To define the behavior of the FPGA, the user provides a design in a [[hardware description language]] (HDL) or as a [[schematic]] design. The HDL form is more suited to work with large structures because it's possible to specify high-level functional behavior rather than drawing every piece by hand. However, schematic entry can allow for easier visualization of a design and its [[Modular programming|component modules]].

Using an [[electronic design automation]] tool, a technology-mapped [[netlist]] is generated. The netlist can then be fit to the actual FPGA architecture using a process called ''[[place and route]]'', usually performed by the FPGA company's proprietary place-and-route software. The user will validate the results using [[timing analysis]], [[simulation]], and other [[verification and validation]] techniques. Once the design and validation process is complete, the binary file generated, typically using the FPGA vendor's proprietary software, is used to (re-)configure the FPGA. This file is transferred to the FPGA via a [[Serial communication|serial interface]] ([[JTAG]]) or to an external memory device such as an [[EEPROM]].<!--[[User:Kvng/RTH]]-->

The most common HDLs are [[VHDL]] and [[Verilog]] as well as extensions such as [[SystemVerilog]]. However, in an attempt to reduce the complexity of designing in HDLs, which have been compared to the equivalent of [[assembly language]]s, there are moves{{by whom|date=July 2015}} to raise the [[abstraction level]] through the introduction of [[Hardware description language#HDL and programming languages|alternative languages]]. [[National Instruments]]' [[LabVIEW]] graphical programming language (sometimes referred to as ''G'') has an FPGA add-in module available to target and program FPGA hardware. [[Verilog]] was created to simplify the process making HDL more robust and flexible. Verilog is currently the most popular. Verilog creates a level of abstraction to hide away the details of its implementation. Verilog has a C-like syntax, unlike VHDL.<ref>{{Cite web|title=Battle Over the FPGA: VHDL vs Verilog! Who is the True Champ?|url=https://blog.digilentinc.com/battle-over-the-fpga-vhdl-vs-verilog-who-is-the-true-champ/|access-date=2020-12-16|website=digilentinc.com|language=en-US|archive-date=2020-12-26|archive-url=https://web.archive.org/web/20201226074106/https://blog.digilentinc.com/battle-over-the-fpga-vhdl-vs-verilog-who-is-the-true-champ/|url-status=dead}}</ref>{{sps|{{subst|DATE}}}}<!--[[User:Kvng/RTH]]-->

To simplify the design of complex systems in FPGAs, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process. These predefined circuits are commonly called ''[[Semiconductor intellectual property core|intellectual property (IP) cores]]'', and are available from FPGA vendors and third-party IP suppliers. They are rarely free, and typically released under proprietary licenses. Other predefined circuits are available from developer communities such as [[OpenCores]] (typically released under [[Free and open-source software|free and open source]] licenses such as the [[GNU General Public License|GPL]], [[BSD license|BSD]] or similar license), and other sources. Such designs are known as [[open-source hardware]].