Intel 5-level paging: Difference between revisions

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{{Use dmy dates|date=August 2018}}

[[File:Page Tables (5 levels).svg|thumb|A diagram of five levels of paging]]

'''Intel 5-level paging''', referred to simply as ''5-level paging'' in [[Intel]] documents, is a processor extension for the [[x86-64]] line of processors to support [[Page table#Multilevel page tables|multilevel page tables]].<ref name="intel-white-paper">{{Cite web|url=https://www.intel.com/content/www/us/en/content-details/671442/5-level-paging-and-5-level-ept-white-paper.html|title=5-Level Paging and 5-Level EPT|publisher=Intel Corporation|date=May 2017}}</ref>{{Rp|11}} It extends the size of [[virtual address]]es from 48&nbsp;bits to 57&nbsp;bits, increasing the addressable [[virtual memory]] from 256&nbsp;[[terabyte|TB]] to 128&nbsp;[[petabyte|PB]].

The extension was first implemented in the [[Ice Lake (microprocessor)|Ice Lake]] processors,<ref name="anandtech-13699">{{Cite web|url=https://www.anandtech.com/show/13699/intel-architecture-day-2018-core-future-hybrid-x86/2|title=Sunny Cove Microarchitecture: A Peek At the Back End|work=Intel's Architecture Day 2018: The Future of Core, Intel GPUs, 10nm, and Hybrid x86|last=Cutress|first=Ian|access-date=2019-10-15}}</ref> and the 4.14 [[Linux kernel]] adds support for it.<ref>{{Cite news|url=https://www.zdnet.com/article/first-linux-4-14-release-adds-very-core-features-arrives-in-time-for-kernels-26th-birthday/|title=First Linux 4.14 release adds "very core" features, arrives in time for kernel's 26th birthday {{!}} ZDNet|last=Tung|first=Liam|work=ZDNet|access-date=2018-04-25|language=en}}</ref> Windows 10 and 11 with server versions also support this extension in their latest updates, where it is provided by a separate kernel of the system called ntkrla57.exe.<ref>{{cite tweet|user=aionescu|number=1142637363840946176|title=Old farts like me will remember the days of ntoskrnl.exe, ntkrnlpa.exe, ntkrnlmp.exe and ntkrpamp.exe.}}</ref>

== Technology ==

In the 4-level paging scheme (previously known as [[IA-32e]] paging), the 64-bit virtual memory address is divided into five parts. The lowest 12 bits contain the offset within the 4 KiB memory page, and the following 36 bits are evenly divided between the four 9 bit descriptors, each linking to a 64-bit [[Page table#Page table entry|page table entry]] in a 512-entry page table for each of the four paging levels. This makes it possible to use bitbits 0 through 47 in the virtual address, for a total of 256&nbsp;TB. <ref name="x86-software-developers-manual" />{{Rp|page=4{{hyp}}2}}

5-level paging adds another 9 bit page table descriptor, making it possible to use bits&nbsp;0 through&nbsp;56. This multiplies the address space by 512 and increases the limit to 128&nbsp;PB.

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With 5-level paging enabled, bits&nbsp;57 through&nbsp;63 must be copies of bit&nbsp;56.<ref name="intel-white-paper" />{{Rp|17}} This is the same as with 4-level paging, where the high-order bits of a virtual address that do not participate in address translation must be the same as the most significant implemented bit.

The 5-level paging is enabled by setting bit 12 of the CR4 register (known as LA57).<ref name="intel-white-paper" />{{Rp|16}} This is only used when the processor is operating in 64 bit mode, and only may be modified when it is not.<ref name="intel-white-paper" />{{Rp|16}} If the bit is not set, or the 5-level paging feature is not supported, the processor uses the 4-level page table structure when operating in 64-bit mode.<ref name="x86-software-developers-manual" />{{Rp|page=4{{hyp}}22}} This is similar to [[Physical Address Extension]] (PAE), where the third level of paging tables to allow 36-bit addressing was enabled by setting a bit in [[Control register#CR4|the CR4 register]].<ref>{{Cite web|url=https://learn.microsoft.com/en-us/previous-versions/windows/hardware/design/dn613969(v=vs.85)|title=Operating Systems and PAE Support - Windows 10 hardware dev|last=Hudek|first=Ted|website=[[Microsoft Learn]]|date=June 2017 |language=en-us|access-date=2024-01-27}}</ref><ref name="x86-software-developers-manual" />{{Rp|page=4{{hyp}}14}}

Future processors may allow full 64-bit virtual address space by extending the size of page table descriptors to 12 bits (4096 page table entries) and memory offset to 16 bits (64 KiB page size) in the 4-level paging scheme or 21 bits (2 MiB page size) in the 5-level scheme.<Ref name=VA64/> Extending page table entry size from 64 to 128 bits would allow arbitrary page sizes, as additional hardware flags would change the size and operation of descriptors on lower paging levels.<Ref name=VA64/>