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{{short description|Processor extension for the x86-64 line of processors}}
{{Use dmy dates|date=August 2018}}
[[File:Page Tables (5 levels).svg|thumb|A diagram of five levels of paging]]▼
'''Intel 5-level paging''', referred to simply as ''5-level paging'' in [[Intel]] documents, is a processor extension for the [[x86-64]] line of processors to support [[Page table#Multilevel page tables|multilevel page tables]].<ref name="intel-white-paper">{{Cite web|url=https://www.intel.com/content/www/us/en/content-details/671442/5-level-paging-and-5-level-ept-white-paper.html|title=5-Level Paging and 5-Level EPT|publisher=Intel Corporation|date=May 2017}}</ref>{{Rp|11}} It extends the size of [[virtual address]]es from 48 bits to 57 bits, increasing the addressable [[virtual memory]] from 256 [[terabyte|TB]] to 128 [[petabyte|PB]]. The extension was first implemented in the [[Ice Lake (microprocessor)|Ice Lake]] processors
== Technology ==
[[File:X86 Paging 64bit.svg|right|555px|4-level paging of the 64-bit mode]]
In the 4-level paging scheme (previously known as [[IA-32e]] paging), the 64-bit virtual memory address is divided into five parts. The lowest 12 bits contain the offset within the 4 KiB memory page, and the following 36 bits are evenly divided between the four 9 bit descriptors, each linking to a 64-bit [[
▲[[File:Page Tables (5 levels).svg|thumb|A diagram of five levels of paging]]
5-level paging adds another 9 bit page table descriptor, making it possible to use bits 0 through 56. This multiplies the address space by 512 and increases the limit to 128 PB.
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5-level paging is implemented by the [[Ice Lake (microprocessor)|Ice Lake]] [[microarchitecture]],<ref name="anandtech-13699"/> [[Epyc#Fourth_generation_Epyc_(Genoa,_Bergamo_and_Siena)|EPYC 9004 Series Processors]]<ref>{{Cite web|url=https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/tuning-guides/58020-epyc-9004-tg-high-perf-toolchain.pdf|title=Tuning Guide for AMD EPYC™ 9004 Processors|publisher=[[AMD]]|date=September 2023}}</ref> and [[List_of_AMD_Ryzen_processors#Storm_Peak_desktop|Storm peak]] [[Ryzen#Threadripper_series|Ryzen Threadripper]] PRO 7900WX series.<ref>{{Cite web|url=https://github.com/InstLatx64/InstLatx64/blob/37bd7b1ac29d95ddcf1fed90efaf7e82c89ab65d/AuthenticAMD/AuthenticAMD0A10F81_K19_StormPeak_01_CPUID.txt#L81C17-L81C25|title=CPUID dump for 96-Core AMD Ryzen Threadripper PRO 7995WX (Storm Peak) Zen4|website=[[GitHub]] |date=October 19, 2023}}</ref>
The 4.14 [[Linux kernel]] adds support for it.<ref>{{Cite news|url=https://www.zdnet.com/article/first-linux-4-14-release-adds-very-core-features-arrives-in-time-for-kernels-26th-birthday/|title=First Linux 4.14 release adds "very core" features, arrives in time for kernel's 26th birthday {{!}} ZDNet|last=Tung|first=Liam|work=ZDNet|access-date=2018-04-25|language=en}}</ref>
Support for the extension was submitted as a set of patches to the [[Linux kernel]] on 8 December 2016.<ref name="phoronix">{{Cite web|url=https://www.phoronix.com/scan.php?page=news_item&px=Intel-5-Level-Paging|title=Intel Working On 5-Level Paging To Increase Linux Virtual/Physical Address Space - Phoronix|author=Michael Larabel|date=9 December 2016|website=[[Phoronix]]|language=en|access-date=2018-04-26}}</ref> As was reported on the [[Linux kernel mailing list]], it consisted of extending the Linux memory model to use five levels rather than four.<ref>{{Cite mailing list|url=http://lkml.iu.edu/hypermail/linux/kernel/1612.1/00383.html|title=[RFC, PATCHv1 00/28] 5-level paging|last=Shutemov|first=Kirill A.|mailing-list=[[Linux kernel mailing list]]|date=December 8, 2016|access-date=2018-04-26}}</ref> This is because, although Linux [[Abstraction (software engineering)|abstracts]] the details of the page tables, it still depends on having a number of levels in its own representation. When an [[Instruction set architecture|architecture]] supports fewer levels, Linux emulates extra levels that do nothing.<ref>{{Cite web|url=https://www.kernel.org/doc/gorman/html/understand/understand006.html|title=Page Table Management|website=www.kernel.org|access-date=2018-04-26}}</ref> A similar change was previously made to extend from three levels to four.<ref>{{Cite web|url=https://lwn.net/Articles/106177/|title=Four-level page tables [LWN.net]|date=October 12, 2004|website=lwn.net|access-date=2018-04-26}}</ref>
Windows 10 and 11 with server versions also support this extension in their latest updates, where it is provided by a separate kernel image called [[ntoskrnl.exe|ntkrla57.exe]].<ref>{{cite tweet|user=aionescu|number=1142637363840946176|title=Old farts like me will remember the days of ntoskrnl.exe, ntkrnlpa.exe, ntkrnlmp.exe and ntkrpamp.exe.}}</ref>
== References ==
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