x86 processors have supported multi-level page tables since the 80386. What the 5-level paging extension does is add support for one *more* level in the page table.
'''Intel 5-level paging''', referred to simply as ''5-level paging'' in [[Intel]] documents, is a processor extension for the [[x86-64]] line of processors to support [[Page table#Multilevel page tables|multilevel page tables]].<ref name="intel-white-paper">{{Cite web|url=https://www.intel.com/content/www/us/en/content-details/671442/5-level-paging-and-5-level-ept-white-paper.html|title=5-Level Paging and 5-Level EPT|publisher=Intel Corporation|date=May 2017}}</ref>{{Rp|11}} It extends the size of [[virtual address]]es from 48 bits to 57 bits, increasing the addressable [[virtual memory]] from 256 [[terabyte|TB]] to 128 [[petabyte|PB]]. The extension was first implemented in the [[Ice Lake (microprocessor)|Ice Lake]] processors.<ref name="anandtech-13699">{{Cite web|url=https://www.anandtech.com/show/13699/intel-architecture-day-2018-core-future-hybrid-x86/2|title=Sunny Cove Microarchitecture: A Peek At the Back End|work=Intel's Architecture Day 2018: The Future of Core, Intel GPUs, 10nm, and Hybrid x86|last=Cutress|first=Ian|access-date=2019-10-15}}</ref>
