Design for testing: Difference between revisions

Revision as of 14:52, 25 February 2024

Revision as of 00:38, 31 December 2024

Line 33:

In both cases, vital information about the nature of the underlying problem may be hidden in the way the chips fail during test. To facilitate better analysis, additional fail information beyond a simple pass/fail is collected into a fail log. The fail log typically contains information about when (e.g., tester cycle), where (e.g., at what tester channel), and how (e.g., logic value) the test failed. Diagnostics attempt to derive from the fail log at which logical/physical ___location inside the chip the problem most likely started. By running a large number of failures through the diagnostics process, called volume diagnostics, systematic failures can be identified.

In some cases (e.g., [[Printedprinted circuit board]]s, [[Multimulti-Chipchip Modulemodule]]s (MCMs), embedded or stand-alone [[Memory (computers)|memories]]) it may be possible to repair a failing circuit under test. For that purpose diagnostics must quickly find the failing unit and create a work-order for repairing/replacing the failing unit.

DFT approaches can be more or less diagnostics-friendly. The related objectives of DFT are to facilitate/simplify fail data collection and diagnostics to an extent that can enable intelligent failure analysis (FA) sample selection, as well as improve the cost, accuracy, speed, and throughput of diagnostics and FA.