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* [[Fuse (electrical)|Fuse]]: one-time programmable. Bipolar. Obsolete.
* [[Antifuse]]: one-time programmable. CMOS. Examples: Actel SX and Axcelerator families; Quicklogic Eclipse II family.<ref name=EDN>{{cite web|url=https://www.edn.com/all-about-fpgas/|title=All about FPGAs|date=21 March 2006 }}</ref>
* [[Programmable read-only memory|PROM]]: programmable read-only memory technology. One-time programmable because of plastic packaging. Obsolete.
* [[EPROM]]: erasable programmable read-only memory technology. One-time programmable but with window, can be erased with ultraviolet (UV) light. CMOS. Obsolete.
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An FPGA can be used to solve any problem which is [[Computability|computable]]. This is trivially proven by the fact that FPGAs can be used to implement a [[soft microprocessor]], such as the Xilinx [[MicroBlaze]] or Altera [[Nios II]]. Their advantage lies in that they are significantly faster for some applications because of their [[Parallel computing|parallel nature]] and [[Logic optimization|optimality]] in terms of the number of gates used for certain processes.<ref name="Xilinx-Inc-Apr-2006-8-K">{{cite web|url=http://edgar.secdatabase.com/657/110465906027899/filing-main.htm |title=Xilinx Inc, Form 8-K, Current Report, Filing Date Apr 26, 2006 |publisher=secdatabase.com |access-date =May 6, 2018}}</ref>
FPGAs originally began as competitors to [[Complex programmable logic device|CPLDs]] to implement [[glue logic]] for [[printed circuit board]]s. As their size, capabilities, and speed increased, FPGAs took over additional functions to the point where some are now marketed as full [[System on a chip|systems on chips]] (SoCs). Particularly with the introduction of dedicated [[Binary multiplier|multiplier]]s into FPGA architectures in the late 1990s, applications which had traditionally been the sole reserve of [[digital signal processor|digital signal processor hardware]] (DSPs) began to incorporate FPGAs instead.<ref>{{cite web|url=https://www.bdti.com/articles/info_eet0207fpga.htm|title=Publications and Presentations|work=bdti.com|access-date=2018-11-02|archive-url=https://web.archive.org/web/20100821182813/http://www.bdti.com/articles/info_eet0207fpga.htm|archive-date=2010-08-21|url-status=dead}}</ref><ref>{{cite web|url=https://www.eetimes.com/xilinx-aims-65-nm-fpgas-at-dsp-applications/#|title=Xilinx aims 65-nm FPGAs at DSP applications|work=EETimes|first=Mark|last=LaPedus|date=5 February 2007 }}</ref>
The evolution of FPGAs has motivated an increase in the use of these devices, whose architecture allows the development of hardware solutions optimized for complex tasks, such as 3D MRI image segmentation, 3D discrete wavelet transform, tomographic image reconstruction, or PET/MRI systems.<ref>{{Cite journal |last1=Alcaín |first1=Eduardo |last2=Fernández |first2=Pedro R. |last3=Nieto |first3=Rubén |last4=Montemayor |first4=Antonio S. |last5=Vilas |first5=Jaime |last6=Galiana-Bordera |first6=Adrian |last7=Martinez-Girones |first7=Pedro Miguel |last8=Prieto-de-la-Lastra |first8=Carmen |last9=Rodriguez-Vila |first9=Borja |last10=Bonet |first10=Marina |last11=Rodriguez-Sanchez |first11=Cristina |date=2021-12-15 |title=Hardware Architectures for Real-Time Medical Imaging |journal=Electronics |language=en |volume=10 |issue=24 |pages=3118 |doi=10.3390/electronics10243118 |issn=2079-9292|doi-access=free }}</ref><ref>{{Cite journal |last1=Nagornov |first1=Nikolay N. |last2=Lyakhov |first2=Pavel A. |last3=Valueva |first3=Maria V. |last4=Bergerman |first4=Maxim V. |date=2022 |title=RNS-Based FPGA Accelerators for High-Quality 3D Medical Image Wavelet Processing Using Scaled Filter Coefficients |journal=IEEE Access |volume=10 |pages=19215–19231 |doi=10.1109/ACCESS.2022.3151361 |s2cid=246895876 |issn=2169-3536|doi-access=free }}</ref> The developed solutions can perform intensive computation tasks with parallel processing, are dynamically reprogrammable, and have a low cost, all while meeting the hard real-time requirements associated with medical imaging.
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