Field-programmable gate array: Difference between revisions

Revision as of 12:41, 11 March 2024

Revision as of 14:19, 12 March 2024

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Using an [[electronic design automation]] tool, a technology-mapped [[netlist]] is generated. The netlist can then be fit to the actual FPGA architecture using a process called ''[[place and route]]'', usually performed by the FPGA company's proprietary place-and-route software. The user will validate the results using [[Static timing analysis|timing analysis]], [[simulation]], and other [[verification and validation]] techniques. Once the design and validation process is complete, the binary file generated, typically using the FPGA vendor's proprietary software, is used to (re-)configure the FPGA. This file is transferred to the FPGA via a [[Serial communication|serial interface]] ([[JTAG]]) or to an external memory device such as an [[EEPROM]].

The most common HDLs are [[VHDL]] and [[Verilog]]. [[National Instruments]]' [[LabVIEW]] graphical programming language (sometimes referred to as ''G'') has an FPGA add-in module available to target and program FPGA hardware. Verilog was created to simplify the process making HDL more robust and flexible. Verilog has a C-like syntax, unlike VHDL.<ref>{{Cite web|title=Battle Over the FPGA: VHDL vs Verilog! Who is the True Champ?|url=https://blog.digilentinc.com/battle-over-the-fpga-vhdl-vs-verilog-who-is-the-true-champ/|access-date=2020-12-16|website=digilentinc.com|language=en-US|archive-date=2020-12-26|archive-url=https://web.archive.org/web/20201226074106/https://blog.digilentinc.com/battle-over-the-fpga-vhdl-vs-verilog-who-is-the-true-champ/|url-status=dead}}</ref>{{sps|{{subst|DATE}}|date=February 2024}}<!--[[User:Kvng/RTH]]-->

To simplify the design of complex systems in FPGAs, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process. These predefined circuits are commonly called ''[[Semiconductor intellectual property core|intellectual property (IP) cores]]'', and are available from FPGA vendors and third-party IP suppliers. They are rarely free, and typically released under proprietary licenses. Other predefined circuits are available from developer communities such as [[OpenCores]] (typically released under [[Free and open-source software|free and open source]] licenses such as the [[GNU General Public License|GPL]], [[BSD license|BSD]] or similar license), and other sources. Such designs are known as [[open-source hardware]].<!--[[User:Kvng/RTH]]-->

In a typical [[Design flow (EDA)|design flow]], an FPGA application developer will simulate the design at multiple stages throughout the design process. Initially the [[Register-transfer level|RTL]] description in [[VHDL]] or [[Verilog]] is simulated by creating [[test bench]]es to simulate the system and observe results. Then, after the [[Logic synthesis|synthesis]] engine has mapped the design to a netlist, the netlist is translated to a [[Logic gate|gate-level]] description where simulation is repeated to confirm the synthesis proceeded without errors. Finally the design is laid out in the FPGA at which point [[propagation delay]]s can be added and the simulation run again with these values [[Back annotation|back-annotated]] onto the netlist.