Contemporary FPGAs have sampleample [[logic gate]]s and RAM blocks to implement complex digital computations. FPGAs can be used to implement any logical function that an [[Application-specific integrated circuit|ASIC]] can perform. The ability to update the functionality after shipping, [[partial re-configuration]] of a portion of the design<ref>{{cite book| last1 = Wisniewski| first1 = Remigiusz| title = Synthesis of compositional microprogram control units for programmable devices| year = 2009| publisher = University of Zielona Góra| ___location = Zielona Góra| isbn = 978-83-7481-293-1| page = 153| url = http://zbc.uz.zgora.pl/Content/27955}}{{Dead link|date=February 2022 |bot=InternetArchiveBot |fix-attempted=yes }}</ref> and the low non-recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications.<ref name="FPGA">{{cite web|url=http://www.eecg.toronto.edu/~vaughn/challenge/fpga_arch.html|title=FPGA Architecture for the Challenge|work=toronto.edu|publisher=[[University of Toronto]]}}</ref>
As FPGA designs employ very fast I/O rates and bidirectional data [[Bus (computing)|buses]], it becomes a challenge to verify correct timing of valid data within setup time and hold time.<ref>{{cite book |last1=Oklobdzija |first1=Vojin G. |title=Digital Design and Fabrication |date=2017 |publisher=CRC Press |isbn=9780849386046 |url=https://books.google.com/books?id=VOnyWUUUj04C&dq=fpga+logic+gates+ram+blocks&pg=SA9-PA6}}</ref> [[Floorplan (microelectronics)|Floor planning]] helps resource allocation within FPGAs to meet these timing constraints.
