Content deleted Content added
→Optional feature instructions: List alias instructions (e.g. CLR Rd is EOR Rd,Rd) in parens after the primary instruction, rather than on a separate line. This reduces the (still too tall) vertical height of this table. |
→Status register: Added Z flag exception for subtract with carry. Reorganized to group it with C flag exception. |
||
Line 169:
===Status register===
The status register bits are:
#<li value=0> C [[Carry flag]]. This is a borrow flag on subtracts.</li>
#<li value=0> C [[Carry flag]]. This is a borrow flag on subtracts. The <code>INC</code> and <code>DEC</code> instructions do ''not'' modify the carry flag, so they may be used to loop over multi-byte arithmetic operations.<ref name="isa_manual">{{cite web |url=http://ww1.microchip.com/downloads/en/devicedoc/atmel-0856-avr-instruction-set-manual.pdf |title=AVR Instruction Set Manual |date=November 2016 |publisher=Atmel |id=Atmel-0856L}}</ref></li>▼
# Z [[Zero flag]]. Set
# N [[Negative flag]]. Set to a copy of the most significant bit of an arithmetic result.
# V [[Overflow flag]]. Set in case of two's complement overflow.
Line 177:
# T Bit copy. Special bit load and bit store instructions use this bit.
# I [[Interrupt flag]]. Set when interrupts are enabled.
There are two special cases which exist to facilitate multi-byte arithmetic:
▲
* The <code>CPC</code>, <code>SBC</code> and <code>SBCI</code> (compare/subtract with carry) instructions do ''not'' set the Z flag when the result is zero, but only clear it if the result is non-zero.{{r|isa_manual|p=79,147,149}} For ''fixed'' precision multi-byte comparisons, implemented with an [[Loop unrolling|unrolled]] <code>CP; CPC; CPC; CPC</code> sequence, this produces a zero flag which is set only if the ''entire'' difference is zero.
== Addressing ==
| |||