Cache (computing): Difference between revisions

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Caches with a [[prefetch input queue]] or more general ''anticipatory paging policy'' go further—they not only read the data requested, but guess that the next chunk or two of data will soon be required, and so prefetch that data into the cache ahead of time. Anticipatory paging is especially helpful when the backing store has a long latency to read the first chunk and much shorter times to sequentially read the next few chunks, such as [[disk storage]] and DRAM.

A few operating systems go further with a [[loader (computing)|loader]] that always pre-loads the entire executable into RAM. A few caches go even further, not only pre-loading an entire file, but also starting to load other related files that may soon be requested, such as the [[page cache]] associated with a [[prefetcher]] or the [[web cache]] associated with [[link prefetching]].<!--[[User:Kvng/RTH]]-->

=={{anchor|HARDWARE}}Examples of hardware caches==

===CPU cache===

{{Main|CPU cache}}

Small memories on or close to the CPU can operate faster than the much larger [[main memory]].<ref>{{Cite journal|last1=Su|first1=Chao|last2=Zeng|first2=Qingkai|date=2021-06-10|editor-last=Nicopolitidis|editor-first=Petros|title=Survey of CPU Cache-Based Side-Channel Attacks: Systematic Analysis, Security Models, and Countermeasures|journal=Security and Communication Networks|language=en|volume=2021|pages=1–15|doi=10.1155/2021/5559552|issn=1939-0122|doi-access=free}}</ref> Most CPUs since the 1980s have used one or more caches, sometimes [[CPU cache#Multi-level caches|in cascaded levels]]; modern high-end [[Embedded computing|embedded]], [[Desktop computer|desktop]] and server [[microprocessor]]s may have as many as six types of cache (between levels and functions).<ref>{{cite web|title=Intel Broadwell Core i7 5775C '128MB L4 Cache' Gaming Behemoth and Skylake Core i7 6700K Flagship Processors Finally Available In Retail|date=25 September 2015|url=https://wccftech.com/intel-broadwell-core-i7-5775c-128mb-l4-cache-and-skylake-core-i7-6700k-flagship-processors-available-retail/}} Mentions L4 cache. Combined with separate I-Cache and TLB, this brings the total 'number of caches (levels+functions) to 6.</ref> Some examples of caches with a specific function are the [[D-cache]], [[I-cache]] and the [[translation lookaside buffer]] for the [[memory management unit]] (MMU).

==={{Anchor|GPU}}GPU cache===

Earlier [[graphics processing unit]]s (GPUs) often had limited read-only [[texture cache]]s, and introducedused [[MortonSwizzling order]](computer [[swizzledgraphics)|Swizzling texture(computer graphics)]]s to improve 2D [[cachelocality coherencyof reference]]. [[Cache miss]]es would drastically affect performance, e.g. if [[mipmapping]] was not used. Caching was important to leverage 32-bit (and wider) transfers for texture data that was often as little as 4&nbsp; bits per pixel, indexed in complex patterns by arbitrary .<!--[[UV coordinatesUser:Kvng/RTH]] and [[perspective transformation]]s in [[inverse texture mapping]].-->

As GPUs advanced (especially with [[GPGPU|General Purpose GPU]] [[compute shader]]s) they have developed progressively larger and increasingly general caches, including [[instruction cache]]s for [[shader]]s, exhibiting increasingly common functionality with CPU caches. For example, [[GeForce 200 series|GT200]] architecture GPUs did not feature an L2 cache, while the GTX 490 GPU has 768&nbsp;KB of last-level cache, the GTX TITAN GPU has 1536&nbsp;KB of last-level cache, and the GTX 980 GPU has 2048&nbsp;KB of last-level cache. These caches have grown to handle [[synchronisation primitive]]s between threads and [[atomic operation]]s, and interface with a CPU-style MMU.