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=== Intel ===
[[Intel]]<ref name="intel_altera">{{cite web |url=https://newsroom.intel.com/news-releases/intel-completes-acquisition-of-altera/ |title=Intel completes acquisition of Altera |work=Intel Newsroom |access-date=15 November 2016}}</ref> supports partial reconfiguration of their FPGA devices on 28 nm devices such as Stratix V,<ref name="stratixv_pr">{{cite web |url=https://www.altera.com/products/fpga/features/stxv-part-reconfig.html |title=Stratix V FPGAs: Ultimate Flexibility Through Partial and Dynamic Reconfiguration |access-date=15 November 2016}}</ref> and on the 20 nm Arria 10 devices.<ref name="arria10_pr">{{cite web |url=https://www.altera.com/products/design-software/fpga-design/quartus-prime/features.html |title=Intel Quartus Prime Software Productivity Tools and Features |access-date=15 November 2016}}</ref> The Intel FPGA partial reconfiguration flow for Arria 10 is based on the hierarchical design methodology in the Quartus Prime Pro software where users create physical partitions of the FPGA that can be reconfigured<ref name="arria10_pr_docs">{{cite web |url=https://www.altera.com/en_US/pdfs/literature/hb/qts/qts-qps-5v1.pdf |title=Quartus Prime Standard Edition Handbook Volume 1: Design and Synthesis |publisher=Intel |access-date=15 November 2016 |pages=4–1}}</ref> at runtime while the remainder of the design continues to operate. The Quartus Prime Pro software also support hierarchical partial reconfiguration and simulation of partial reconfiguration.
== Classification of systems ==
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