Microcode: Difference between revisions

Revision as of 12:00, 28 June 2024

Revision as of 17:57, 28 July 2024

Line 13:

==Overview==

===Instruction sets===

At the hardware level, processors contain a number of separate areas of circuitycircuitry, or "units", that perform different tasks. Commonly found units include the [[arithmetic logic unit]] (ALU) which performs instructions such as addition or comparing two numbers, circuits for reading and writing data to external memory, and small areas of onboard memory to store these values while they are being processed. In most designs, additional high-performance memory, the [[register file]], is used to store temporary values, not just those needed by the current instruction.<ref name=CPU>{{cite web |url=https://www.redhat.com/sysadmin/cpu-components-functionality |title=The central processing unit (CPU): Its components and functionality |website=Red Hat |first=David |last=Both |date=23 July 2020}}</ref>

To properly perform an instruction, the various circuits have to be activated in order. For instance, it is not possible to add two numbers if they have not yet been loaded from memory. In [[RISC]] designs, the proper ordering of these instructions is largely up to the programmer, or at least to the [[compiler]] of the [[programming language]] they are using. So to add two numbers, for instance, the compiler may output instructions to load one of the values into one register, the second into another, call the addition function in the ALU, and then write the result back out to memory.<ref name=CPU/>

Line 33:

===Design===

Engineers normally write the microcode during the design phase of a processor, storing it in a [[read-only memory]] (ROM) or [[programmable logic array]] (PLA)<ref>{{cite journal |last1=Manning |first1=B.M. |last2=Mitby |first2=J.S |last3=Nicholson |first3=J.O. |title=Microprogrammed Processor Having PLA Control Store |journal=IBM Technical Disclosure Bulletin |volume=22 |issue=6 |date=November 1979 |url=http://www.computerhistory.org/collections/accession/102660026 |access-date=2011-07-10 |url-status=live |archive-url=https://web.archive.org/web/20121001165413/http://www.computerhistory.org/collections/accession/102660026 |archive-date=2012-10-01}}</ref> structure, or in a combination of both.<ref>Often denoted a ROM/PLA control store in the context of usage in a CPU; {{cite web |last=Supnik |first=Bob |date=24 February 2008 |title=J-11: DEC's fourth and last PDP-11 microprocessor design ... features ... ROM/PLA control store |url=http://simh.trailing-edge.com/semi/j11.html |access-date=2011-07-10 |url-status=live |archive-url=https://web.archive.org/web/20110709032923/http://simh.trailing-edge.com/semi/j11.html |archive-date=2011-07-09}}</ref> However, machines also exist that have some or all microcode stored in [[static random-access memory]] (SRAM) or [[flash memory]]. This is traditionally denoted as ''writeablewritable [[control store]]'' in the context of computers, which can be either read-only or [[read–write memory]]. In the latter case, the CPU initialization process loads microcode into the control store from another storage medium, with the possibility of altering the microcode to correct bugs in the instruction set, or to implement new machine instructions.

===Microprograms===

Line 109:

The industry responded to the concept of RISC with both confusion and hostility, including a famous dismissive article by the VAX team at Digital.<ref name=comments>{{cite journal |url=https://dl.acm.org/doi/pdf/10.1145/641914.641918 |title=Comments on "The Case for the Reduced Instruction Computer" |first1=Douglas |last1=Clark |first2=William |last2=Strecker |date=September 1980 |journal=ACM|volume=8 |issue=6 |pages=34–38 |doi=10.1145/641914.641918 |s2cid=14939489 }}</ref> A major point of contention was that implementing the instructions outside of the processor meant it would spend much more time reading those instructions from memory, thereby slowing overall performance no matter how fast the CPU itself ran.<ref name=comments/> Proponents pointed out that simulations clearly showed the number of instructions was not much greater, especially when considering compiled code.<ref name=risc/>

The debate raged until the first commercial RISC designs emerged in the second half of the 1980s, which easily outperformed the most complex designs from other companies. By the late 1980s it was over; even DEC was abandoning microcode for their [[DEC Alpha]] designs, and CISC processors switched to using hardwired circuitry, rather than microcode, to perform many functions. For example, the [[Intel 80486]] uses hardwired circuitry to fetch and decode instructions, using microcode only to execute instructions; register-register move and arithmetic instructions required only one microinstruction, allowing them to be completed in one clock cycle.<ref>{{cite conference|url=https://ieeexplore.ieee.org/document/63682|title=The execution pipeline of the Intel i486 CPU|book-title= Digest of Papers Compcon Spring '90. Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage|publisher=[[IEEE]]|isbn=0-8186-2028-5|___location=San Francisco, CA|doi=10.1109/CMPCON.1990.63682}}</ref> The [[Pentium Pro]]'s fetch and decode hardware fetches instructions and decodes them into series of micro-operations that are passed on to the execution unit, which schedules and executes the micro-operations, possibly doing so [[out-of-order execution|out-of-order]]. Complex instructions are implemented by microcode that consists of pre-definedpredefined sequences of micro-operations.<ref>{{cite web|url=http://stffrdhrn.github.io/content/2019/Intel_PentiumPro.pdf|title=Pentium Pro Processor At 150, 166, 180, and 200 MHz|publisher=[[Intel]]|date=November 1995|type=Datasheet}}</ref>

Some processor designs use machine code that runs in a special mode, with special instructions, available only in that mode, that have access to processor-dependent hardware, to implement some low-level features of the instruction set. The DEC Alpha, a pure RISC design, used [[PALcode]] to implement features such as [[translation lookaside buffer]] (TLB) miss handling and interrupt handling,<ref name="axp-architecture-manual">{{cite book|url=http://bitsavers.org/pdf/dec/alpha/Sites_AlphaAXPArchitectureReferenceManual_2ed_1995.pdf|title=Alpha AXP Architecture Reference Manual|edition=Second|chapter=Part I / Common Architecture, Chapter 6 Common PALcode Architecture|publisher=[[Digital Press]]|date=1995|isbn=1-55558-145-5}}</ref> as well as providing, for Alpha-based systems running [[OpenVMS]], instructions requiring interlocked memory accesaccess that are similar to instructions provided by the [[VAX]] architecture.<ref name="axp-architecture-manual" /> CMOS [[IBM System/390]] CPUs, starting with the G4 processor, and [[z/Architecture]] CPUs use [[millicode]] to implement some instructions.<ref>{{cite journal|last=Rogers|first=Bob|title=The What and Why of zEnterprise Millicode|journal=IBM Systems Magazine|date=Sep–Oct 2012|url=http://www.ibmsystemsmag.com/mainframe/administrator/performance/millicode_rogers/|archive-url=https://web.archive.org/web/20121009085728/http://www.ibmsystemsmag.com/mainframe/administrator/performance/millicode_rogers/|archive-date=October 9, 2012|url-status=dead}}</ref>

==Examples==

Line 223:

A few computers were built using ''writable microcode''. In this design, rather than storing the microcode in ROM or hard-wired logic, the microcode is stored in a RAM called a ''writable control store'' or ''WCS''. Such a computer is sometimes called a ''writable instruction set computer'' (WISC).<ref>{{cite journal |last=Koopman |first=Philip Jr. |date=1987 |url=http://www.ece.cmu.edu/~koopman/forth/rochester_87.pdf |title=Writable instruction set, stack oriented computers: The WISC Concept |journal=The Journal of Forth Application and Research |pages=49–71 |url-status=live |archive-url=https://web.archive.org/web/20080511192958/http://www.ece.cmu.edu/~koopman/forth/rochester_87.pdf |archive-date=2008-05-11}}</ref>

Many experimental prototype computers use [[#Writable control store|writable control stores]]; there are also commercial machines that use writable microcode, such as the [[Burroughs Small Systems]], early [[Xerox PARC|Xerox]] workstations, the [[Digital Equipment Corporation|DEC]] [[VAX]] 8800 (''Nautilus'') family, the [[Symbolics]] L- and G-machines, a number of IBM System/360 and [[System/370]] implementations, some DEC [[PDP-10]] machines,<ref>{{cite newsgroup |last=Smith |first=Eric |date=3 September 2002 |url=http://pdp10.nocrew.org/cpu/kl10-ucode.txt |title=Re: What was the size of Microcode in various machines |message-id=[e-mail] |newsgroup=alt.folklore.computers |access-date=18 December 2008 |url-status=live |archive-url=https://web.archive.org/web/20090126231132/http://pdp10.nocrew.org/cpu/kl10-ucode.txt |archive-date=26 January 2009}}</ref> and the [[Data General Eclipse MV/8000]].<ref>{{cite web |last=Smotherman |first=Mark |title=CPSC 3300 / The Soul of a New Machine |url=https://people.computing.clemson.edu/~mark/330/eagle.html |quote=4096 x 75-bit SRAM writeablewritable control store: 74-bit microinstruction with 1 parity bit (18 fields) |access-date=2023-10-27}}</ref>

The IBM System/370 includes a facility called ''Initial-Microprogram Load'' (''IML'' or ''IMPL'')<ref>{{cite book